Alfredo Bermudez Lozada

Array ( [id] => 11315692 [patent_doc_number] => 20160351802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'NONLINEAR DIELECTRIC STACK CIRCUIT ELEMENT' [patent_app_type] => utility [patent_app_number] => 15/111515 [patent_app_country] => US [patent_app_date] => 2014-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5895 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15111515 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10239545 [patent_doc_number] => 20150124540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/164897 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3360 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14164897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10321589 [patent_doc_number] => 20150206594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'FUSE CIRCUIT WITH TEST MODE' [patent_app_type] => utility [patent_app_number] => 14/161927 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10321572 [patent_doc_number] => 20150206576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'NEGATIVE BIT LINE WRITE ASSIST FOR MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 14/160706 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14160706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14521789 [patent_doc_number] => 10338146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Method for determining a control observer for the SoC [patent_app_type] => utility [patent_app_number] => 14/762719 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5683 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14762719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10551104 [patent_doc_number] => 09275735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits' [patent_app_type] => utility [patent_app_number] => 14/148083 [patent_app_country] => US [patent_app_date] => 2014-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4901 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14148083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10575561 [patent_doc_number] => 09298201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Power delivery to three-dimensional chips' [patent_app_type] => utility [patent_app_number] => 14/132506 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3701 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10258029 [patent_doc_number] => 20150143026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'TEMPERATURE BASED FLASH MEMORY SYSTEM MAINTENANCE' [patent_app_type] => utility [patent_app_number] => 14/086355 [patent_app_country] => US [patent_app_date] => 2013-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6618 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13769017 [patent_doc_number] => 10176855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Three-dimensional (3-D) write assist scheme for memory cells [patent_app_type] => utility [patent_app_number] => 14/086153 [patent_app_country] => US [patent_app_date] => 2013-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13185 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10253909 [patent_doc_number] => 20150138905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'Low Leakage State Retention Synchronizer' [patent_app_type] => utility [patent_app_number] => 14/083185 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10802516 [patent_doc_number] => 20160148673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'FIRST DATA IN RESPONSE TO SECOND READ REQUEST' [patent_app_type] => utility [patent_app_number] => 14/897385 [patent_app_country] => US [patent_app_date] => 2013-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4597 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14897385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9329270 [patent_doc_number] => 20140056052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'RESISTIVE MEMORY DEVICE PERFORMING SELECTIVE REFRESH AND METHOD OF REFRESHING RESISTIVE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/925177 [patent_app_country] => US [patent_app_date] => 2013-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9210824 [patent_doc_number] => 20140010001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING MEMORY CELL WITH ELECTROSTATIC CAPACITANCE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/922773 [patent_app_country] => US [patent_app_date] => 2013-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10877 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13922773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12553545 [patent_doc_number] => 10014070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Data path integrity verification in memory devices [patent_app_type] => utility [patent_app_number] => 13/919135 [patent_app_country] => US [patent_app_date] => 2013-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3793 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13919135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11279558 [patent_doc_number] => 09496039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Storage device and method for performing interruption control thereof' [patent_app_type] => utility [patent_app_number] => 14/408535 [patent_app_country] => US [patent_app_date] => 2013-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 32 [patent_no_of_words] => 22795 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 389 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14408535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10631296 [patent_doc_number] => 09349450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-24 [patent_title] => 'Memory devices and memory operational methods including single erase operation of conductive bridge memory cells' [patent_app_type] => utility [patent_app_number] => 13/914415 [patent_app_country] => US [patent_app_date] => 2013-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 5323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13914415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9770019 [patent_doc_number] => 20140293682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'MEMORY BITCELL CLUSTERS EMPLOYING LOCALIZED GENERATION OF COMPLEMENTARY BITLINES TO REDUCE MEMORY AREA, AND RELATED SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/910215 [patent_app_country] => US [patent_app_date] => 2013-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8952 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13910215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9180202 [patent_doc_number] => 20130322187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-05 [patent_title] => 'SEMICONDUCTOR DEVICE AND PROCESSING UNIT' [patent_app_type] => utility [patent_app_number] => 13/904383 [patent_app_country] => US [patent_app_date] => 2013-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13904383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9210855 [patent_doc_number] => 20140010032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'Read-Current and Word Line Delay Path Tracking for Sense Amplifier Enable Timing' [patent_app_type] => utility [patent_app_number] => 13/898803 [patent_app_country] => US [patent_app_date] => 2013-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9125 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13898803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9160126 [patent_doc_number] => 20130308403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/895195 [patent_app_country] => US [patent_app_date] => 2013-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5925 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895195 [rel_patent_id] =>[rel_patent_doc_number] =>)