Search

Alfredo Bermudez Lozada

Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
617
Issued Applications
490
Pending Applications
86
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9203960 [patent_doc_number] => 20140003137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'DETERMINING DEVICE AND DETERMINING METHOD' [patent_app_type] => utility [patent_app_number] => 13/870301 [patent_app_country] => US [patent_app_date] => 2013-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9465 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13870301 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/870301
DETERMINING DEVICE AND DETERMINING METHOD Apr 24, 2013 Abandoned
Array ( [id] => 9196731 [patent_doc_number] => 20130336047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'Cell Refresh in Phase Change Memory' [patent_app_type] => utility [patent_app_number] => 13/869065 [patent_app_country] => US [patent_app_date] => 2013-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8170 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13869065 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/869065
Cell Refresh in Phase Change Memory Apr 23, 2013 Abandoned
Array ( [id] => 10066476 [patent_doc_number] => 09105330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-08-11 [patent_title] => 'Memory devices configured to apply different weights to different strings of memory cells coupled to a data line and methods' [patent_app_type] => utility [patent_app_number] => 13/864659 [patent_app_country] => US [patent_app_date] => 2013-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 20008 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13864659 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/864659
Memory devices configured to apply different weights to different strings of memory cells coupled to a data line and methods Apr 16, 2013 Issued
Array ( [id] => 10651931 [patent_doc_number] => 09368193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Methods for reducing power dissipation in drowsy caches and for retaining data in cache-memory sleep mode' [patent_app_type] => utility [patent_app_number] => 13/856425 [patent_app_country] => US [patent_app_date] => 2013-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8533 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13856425 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/856425
Methods for reducing power dissipation in drowsy caches and for retaining data in cache-memory sleep mode Apr 2, 2013 Issued
Array ( [id] => 9119826 [patent_doc_number] => 20130286748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'NONVOLATILE SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/847201 [patent_app_country] => US [patent_app_date] => 2013-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13847201 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/847201
NAND flash memory employing bit line charge/discharge circuit Mar 18, 2013 Issued
Array ( [id] => 9173011 [patent_doc_number] => 20130314996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'NONVOLATILE SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/847085 [patent_app_country] => US [patent_app_date] => 2013-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13847085 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/847085
Nonvolatile semiconductor storage device Mar 18, 2013 Issued
Array ( [id] => 9261195 [patent_doc_number] => 20130343124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD FOR SAME' [patent_app_type] => utility [patent_app_number] => 13/845509 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12033 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13845509 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/845509
SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD FOR SAME Mar 17, 2013 Abandoned
Array ( [id] => 9544449 [patent_doc_number] => 20140169096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/846855 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6717 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13846855 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/846855
Semiconductor memory device with high threshold voltage distribution reliability method Mar 17, 2013 Issued
Array ( [id] => 9146832 [patent_doc_number] => 20130301355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'EEPROM MEMORY UNIT AND EEPROM MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/846549 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1886 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13846549 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/846549
EEPROM MEMORY UNIT AND EEPROM MEMORY DEVICE Mar 17, 2013 Abandoned
Array ( [id] => 9461859 [patent_doc_number] => 20140126285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/846599 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9117 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13846599 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/846599
Semiconductor memory device and operating method based upon a comparison of program data and read data thereof Mar 17, 2013 Issued
Array ( [id] => 9567668 [patent_doc_number] => 20140185381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'SEMICONDUCTOR APPARATUS AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/846873 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7012 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13846873 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/846873
SEMICONDUCTOR APPARATUS AND METHOD OF OPERATING THE SAME Mar 17, 2013 Abandoned
Array ( [id] => 11200854 [patent_doc_number] => 09431072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'On-the-fly trimmable sense amplifier' [patent_app_type] => utility [patent_app_number] => 14/386815 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3129 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14386815 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/386815
On-the-fly trimmable sense amplifier Mar 14, 2013 Issued
Array ( [id] => 12435744 [patent_doc_number] => 09978430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Memory devices providing a refresh request and memory controllers responsive to a refresh request [patent_app_type] => utility [patent_app_number] => 13/733884 [patent_app_country] => US [patent_app_date] => 2013-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 17859 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733884 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733884
Memory devices providing a refresh request and memory controllers responsive to a refresh request Jan 2, 2013 Issued
Array ( [id] => 9329310 [patent_doc_number] => 20140056092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/720249 [patent_app_country] => US [patent_app_date] => 2012-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4899 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13720249 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/720249
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME Dec 18, 2012 Abandoned
Array ( [id] => 10028571 [patent_doc_number] => 09070476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Refresh circuits' [patent_app_type] => utility [patent_app_number] => 13/716041 [patent_app_country] => US [patent_app_date] => 2012-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8632 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13716041 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/716041
Refresh circuits Dec 13, 2012 Issued
Array ( [id] => 9133472 [patent_doc_number] => 20130294186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'PHASE-LOCKED LOOP AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME, AND TEST SYSTEM INCLUDING THE INTEGRATED CIRCUIT CHIP' [patent_app_type] => utility [patent_app_number] => 13/714357 [patent_app_country] => US [patent_app_date] => 2012-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5489 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13714357 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/714357
Phase-locked loop and integrated circuit chip including the same, and test system including the integrated circuit chip Dec 12, 2012 Issued
Array ( [id] => 12573336 [patent_doc_number] => 10020036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Address bit remapping scheme to reduce access granularity of DRAM accesses [patent_app_type] => utility [patent_app_number] => 13/712823 [patent_app_country] => US [patent_app_date] => 2012-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6306 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13712823 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/712823
Address bit remapping scheme to reduce access granularity of DRAM accesses Dec 11, 2012 Issued
Array ( [id] => 13754471 [patent_doc_number] => 10170187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Apparatuses and methods using negative voltages in part of memory write read, and erase operations [patent_app_type] => utility [patent_app_number] => 13/437547 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8113 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437547 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437547
Apparatuses and methods using negative voltages in part of memory write read, and erase operations Apr 1, 2012 Issued
Array ( [id] => 10512651 [patent_doc_number] => 09240229 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-19 [patent_title] => 'Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode' [patent_app_type] => utility [patent_app_number] => 13/421812 [patent_app_country] => US [patent_app_date] => 2012-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7733 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13421812 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/421812
Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode Mar 14, 2012 Issued
Array ( [id] => 9296968 [patent_doc_number] => 20140040602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'Storage Method, Memory, and Storing System with Accumulated Write Feature' [patent_app_type] => utility [patent_app_number] => 14/003808 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5423 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14003808 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/003808
Storage Method, Memory, and Storing System with Accumulated Write Feature Dec 29, 2011 Abandoned
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