Search

Alfredo Bermudez Lozada

Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
617
Issued Applications
490
Pending Applications
86
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20189566 [patent_doc_number] => 12400688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Assemblies comprising memory cells and select gates; and methods of forming assemblies [patent_app_type] => utility [patent_app_number] => 18/438709 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2131 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438709 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438709
Assemblies comprising memory cells and select gates; and methods of forming assemblies Feb 11, 2024 Issued
Array ( [id] => 20204452 [patent_doc_number] => 12407241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Power management integrated circuit with charge pump [patent_app_type] => utility [patent_app_number] => 18/435134 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1079 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435134 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435134
Power management integrated circuit with charge pump Feb 6, 2024 Issued
Array ( [id] => 19193529 [patent_doc_number] => 20240172442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SEMICONDUCTOR MEMORY DEVICE WITH THREE-DIMENSIONAL MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/422092 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 594 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18422092 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/422092
Semiconductor memory device with three-dimensional memory cells Jan 24, 2024 Issued
Array ( [id] => 19835485 [patent_doc_number] => 20250087271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/411348 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411348 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411348
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE Jan 11, 2024 Pending
Array ( [id] => 19160848 [patent_doc_number] => 20240153555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => CAMS FOR LOW LATENCY COMPLEX DISTRIBUTION SAMPLING [patent_app_type] => utility [patent_app_number] => 18/411222 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411222 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411222
CAMs for low latency complex distribution sampling Jan 11, 2024 Issued
Array ( [id] => 19335346 [patent_doc_number] => 20240249776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => DRAIN-SIDE WORDLINE VOLTAGE BOOSTING TO REDUCE LATERAL ELECTRON FIELD DURING A PROGRAMMING OPERATION [patent_app_type] => utility [patent_app_number] => 18/411532 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411532 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411532
Drain-side wordline voltage boosting to reduce lateral electron field during a programming operation Jan 11, 2024 Issued
Array ( [id] => 19986780 [patent_doc_number] => 20250125002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => ELECTRONIC SYSTEM RELATED TO DETECTING A RESULT OF A RUPTURE OPERATION [patent_app_type] => utility [patent_app_number] => 18/411412 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411412 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411412
ELECTRONIC SYSTEM RELATED TO DETECTING A RESULT OF A RUPTURE OPERATION Jan 11, 2024 Pending
Array ( [id] => 19696102 [patent_doc_number] => 20250014647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => STORAGE DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/408126 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408126 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408126
STORAGE DEVICE AND METHOD OF OPERATING THE SAME Jan 8, 2024 Pending
Array ( [id] => 19305270 [patent_doc_number] => 20240233850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => WORDLINE DEFECT DETECTION CIRCUIT, WORDLINE DEFECT DETECTION METHOD, AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/403091 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12926 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403091
WORDLINE DEFECT DETECTION CIRCUIT, WORDLINE DEFECT DETECTION METHOD, AND MEMORY DEVICE INCLUDING THE SAME Jan 2, 2024 Pending
Array ( [id] => 20416678 [patent_doc_number] => 12499968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Semiconductor device having fuse array [patent_app_type] => utility [patent_app_number] => 18/402096 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402096
Semiconductor device having fuse array Jan 1, 2024 Issued
Array ( [id] => 20071849 [patent_doc_number] => 20250210071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => SUPERBLOCK-BASED PROGRAMMING-TEMPERATURE AWARENESS IN STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 18/396611 [patent_app_country] => US [patent_app_date] => 2023-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18396611 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/396611
SUPERBLOCK-BASED PROGRAMMING-TEMPERATURE AWARENESS IN STORAGE DEVICES Dec 25, 2023 Pending
Array ( [id] => 19696111 [patent_doc_number] => 20250014656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => OPERATION METHOD FOR MEMORY, MEMORY, MEMORY SYSTEM AND ELECTRONIC SYSTEM [patent_app_type] => utility [patent_app_number] => 18/395336 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395336 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395336
OPERATION METHOD FOR MEMORY, MEMORY, MEMORY SYSTEM AND ELECTRONIC SYSTEM Dec 21, 2023 Pending
Array ( [id] => 19252483 [patent_doc_number] => 20240203480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => MEMORY POWER CONTROL UNIT [patent_app_type] => utility [patent_app_number] => 18/535443 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18535443 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/535443
Memory power control unit Dec 10, 2023 Issued
Array ( [id] => 19271508 [patent_doc_number] => 20240215215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY DEVICE INCLUDING VERTICAL CHANNEL TRANSISTOR AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/534220 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534220 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534220
MEMORY DEVICE INCLUDING VERTICAL CHANNEL TRANSISTOR AND ELECTRONIC DEVICE INCLUDING THE SAME Dec 7, 2023 Pending
Array ( [id] => 19239437 [patent_doc_number] => 20240196633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MEMORY DEVICE AND SYSTEM HAVING MULTIPLE PHYSICAL INTERFACES [patent_app_type] => utility [patent_app_number] => 18/529365 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529365 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/529365
MEMORY DEVICE AND SYSTEM HAVING MULTIPLE PHYSICAL INTERFACES Dec 4, 2023 Pending
Array ( [id] => 19054464 [patent_doc_number] => 20240096433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => WEIGHTED WEAR LEVELING FOR IMPROVING UNIFORMITY [patent_app_type] => utility [patent_app_number] => 18/521382 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521382
WEIGHTED WEAR LEVELING FOR IMPROVING UNIFORMITY Nov 27, 2023 Pending
Array ( [id] => 20718111 [patent_doc_number] => 12633367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Storage device and operating method of controller of storage device based on program operation control [patent_app_type] => utility [patent_app_number] => 18/510664 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18510664 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/510664
Storage device and operating method of controller of storage device based on program operation control Nov 15, 2023 Issued
Array ( [id] => 19175872 [patent_doc_number] => 20240161846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => TRIM SETTING DETERMINATION FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/389140 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/389140
Trim setting determination for a memory device Nov 12, 2023 Issued
Array ( [id] => 20215959 [patent_doc_number] => 12412613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Energy-efficient memory for cryogenic computing [patent_app_type] => utility [patent_app_number] => 18/505128 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 603 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505128 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505128
Energy-efficient memory for cryogenic computing Nov 8, 2023 Issued
Array ( [id] => 19192265 [patent_doc_number] => 20240171178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/504072 [patent_app_country] => US [patent_app_date] => 2023-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18504072 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/504072
Configuration latch for programmable logic device Nov 6, 2023 Issued
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