Search

Alfredo Bermudez Lozada

Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
617
Issued Applications
490
Pending Applications
86
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20416663 [patent_doc_number] => 12499953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Wipe-out and verification of a non-volatile memory [patent_app_type] => utility [patent_app_number] => 18/500150 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1231 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18500150 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/500150
Wipe-out and verification of a non-volatile memory Nov 1, 2023 Issued
Array ( [id] => 20538561 [patent_doc_number] => 12555640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Suppression of peak ICC during block selection in non-volatile memories [patent_app_type] => utility [patent_app_number] => 18/492545 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 43 [patent_no_of_words] => 22166 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18492545 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/492545
Suppression of peak ICC during block selection in non-volatile memories Oct 22, 2023 Issued
Array ( [id] => 19305259 [patent_doc_number] => 20240233839 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => COMPACT DIGITAL THERMOMETER IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/489770 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489770 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489770
Compact digital thermometer in a memory device Oct 17, 2023 Issued
Array ( [id] => 19305259 [patent_doc_number] => 20240233839 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => COMPACT DIGITAL THERMOMETER IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/489770 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489770 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489770
Compact digital thermometer in a memory device Oct 17, 2023 Issued
Array ( [id] => 20564847 [patent_doc_number] => 12567461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Memory device and operation to reduce impact of parasitic wire resistance and capacitance [patent_app_type] => utility [patent_app_number] => 18/378598 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378598 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/378598
Memory device and operation to reduce impact of parasitic wire resistance and capacitance Oct 9, 2023 Issued
Array ( [id] => 19269029 [patent_doc_number] => 20240212733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => METHODS AND CIRCUITS FOR READING AND WRITING PI-STATE-INDUCED CIRCULATING CURRENTS INTO SUPERCONDUCTING CIRCUITS CONTAINING MAGNETIC JOSEPHSON JUNCTIONS [patent_app_type] => utility [patent_app_number] => 18/478140 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/478140
METHODS AND CIRCUITS FOR READING AND WRITING PI-STATE-INDUCED CIRCULATING CURRENTS INTO SUPERCONDUCTING CIRCUITS CONTAINING MAGNETIC JOSEPHSON JUNCTIONS Sep 28, 2023 Pending
Array ( [id] => 19765723 [patent_doc_number] => 12224021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Memory device with leakage current verifying circuit for minimizing leakage current [patent_app_type] => utility [patent_app_number] => 18/469567 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5342 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 529 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469567 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/469567
Memory device with leakage current verifying circuit for minimizing leakage current Sep 18, 2023 Issued
Array ( [id] => 20820730 [patent_doc_number] => 12676203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-07 [patent_title] => Appratus and method for changing a read voltage applied for reading data from a non-volatile memory cell [patent_app_type] => utility [patent_app_number] => 18/469562 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8394 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469562 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/469562
Appratus and method for changing a read voltage applied for reading data from a non-volatile memory cell Sep 18, 2023 Issued
Array ( [id] => 19850387 [patent_doc_number] => 20250095738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => THRESHOLD VOLTAGE BUDGET BY EMPLOYING AN OXIDE-NITRIDE PITCH DEPENDENT THRESHOLD VOLTAGE WINDOW [patent_app_type] => utility [patent_app_number] => 18/369028 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18369028 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/369028
THRESHOLD VOLTAGE BUDGET BY EMPLOYING AN OXIDE-NITRIDE PITCH DEPENDENT THRESHOLD VOLTAGE WINDOW Sep 14, 2023 Pending
Array ( [id] => 20132081 [patent_doc_number] => 12374398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Forming operation of resistive memory device [patent_app_type] => utility [patent_app_number] => 18/457377 [patent_app_country] => US [patent_app_date] => 2023-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18457377 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/457377
Forming operation of resistive memory device Aug 28, 2023 Issued
Array ( [id] => 19531475 [patent_doc_number] => 20240355377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => MEMORY DEVICE FOR SELF-SEARCHING FOR BOUNDARY WORD LINE, METHOD FOR OPERATING MEMORY DEVICE, AND MEMORY SYSTEM INCLUDING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/455625 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455625 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/455625
MEMORY DEVICE FOR SELF-SEARCHING FOR BOUNDARY WORD LINE, METHOD FOR OPERATING MEMORY DEVICE, AND MEMORY SYSTEM INCLUDING MEMORY DEVICE Aug 24, 2023 Pending
Array ( [id] => 18820837 [patent_doc_number] => 20230395178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => CONTROLLING MEMORY INCLUDING MANAGING A CORRECTION VALUE TABLE [patent_app_type] => utility [patent_app_number] => 18/453567 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453567 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/453567
Controlling memory including managing a correction value table Aug 21, 2023 Issued
Array ( [id] => 18820797 [patent_doc_number] => 20230395138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => Systems and Methods for Reducing Standby Power in Floating Body Memory Devices [patent_app_type] => utility [patent_app_number] => 18/235478 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235478 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/235478
Systems and Methods for Reducing Standby Power in Floating Body Memory Devices Aug 17, 2023 Pending
Array ( [id] => 20203963 [patent_doc_number] => 12406746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Semiconductor storage apparatus capable of efficiently performing screening test [patent_app_type] => utility [patent_app_number] => 18/451113 [patent_app_country] => US [patent_app_date] => 2023-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 1193 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451113
Semiconductor storage apparatus capable of efficiently performing screening test Aug 16, 2023 Issued
Array ( [id] => 20758850 [patent_doc_number] => 12651627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Peripheral structure arrangements of memory devices and methods for forming the same [patent_app_type] => utility [patent_app_number] => 18/234333 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 6758 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18234333 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/234333
Peripheral structure arrangements of memory devices and methods for forming the same Aug 14, 2023 Issued
Array ( [id] => 19687699 [patent_doc_number] => 20250006244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => ASYMMETRIC PASS VOLTAGE SCHEME FOR NON-VOLATILE MEMORY APPARATUS SIZE REDUCTION [patent_app_type] => utility [patent_app_number] => 18/233640 [patent_app_country] => US [patent_app_date] => 2023-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18233640 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/233640
ASYMMETRIC PASS VOLTAGE SCHEME FOR NON-VOLATILE MEMORY APPARATUS SIZE REDUCTION Aug 13, 2023 Pending
Array ( [id] => 19773110 [patent_doc_number] => 20250054536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/448479 [patent_app_country] => US [patent_app_date] => 2023-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448479 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448479
Memory device adjusting reference voltage signal Aug 10, 2023 Issued
Array ( [id] => 19191173 [patent_doc_number] => 20240170086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => METHOD FOR OPERATING A MEMORY DEVICE AND MEMORY DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 18/360530 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360530 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360530
Method for operating a memory device and memory device thereof Jul 26, 2023 Issued
Array ( [id] => 19269078 [patent_doc_number] => 20240212782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY CONTROLLER, AN OPERATION METHOD THEREOF, A MEMORY DEVICE, AND A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/226340 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226340
MEMORY CONTROLLER, AN OPERATION METHOD THEREOF, A MEMORY DEVICE, AND A MEMORY SYSTEM Jul 25, 2023 Pending
Array ( [id] => 20667392 [patent_doc_number] => 12609172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Non-volatile memory with intelligent erase testing to avoid neighbor plane disturb [patent_app_type] => utility [patent_app_number] => 18/358651 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 33 [patent_no_of_words] => 18452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358651 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358651
Non-volatile memory with intelligent erase testing to avoid neighbor plane disturb Jul 24, 2023 Issued
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