Search

Alfredo Bermudez Lozada

Examiner (ID: 7463, Phone: (571)272-0877 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
617
Issued Applications
490
Pending Applications
86
Abandoned Applications
57

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20581205 [patent_doc_number] => 12573459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Semiconductor storage device having depletion-type memory cell transistors [patent_app_type] => utility [patent_app_number] => 18/177115 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2468 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177115 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/177115
Semiconductor storage device having depletion-type memory cell transistors Mar 1, 2023 Issued
Array ( [id] => 20581211 [patent_doc_number] => 12573465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Error correction code circuit and semiconductor apparatus including the error correction code circuit [patent_app_type] => utility [patent_app_number] => 18/104907 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 1040 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104907 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104907
Error correction code circuit and semiconductor apparatus including the error correction code circuit Feb 1, 2023 Issued
Array ( [id] => 19835486 [patent_doc_number] => 20250087272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => METHOD FOR OPERATING FERROELECTRIC-BASED THREE-DIMENSIONAL FLASH MEMORY INCLUDING DATA STORAGE PATTERN [patent_app_type] => utility [patent_app_number] => 18/725991 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18725991 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/725991
METHOD FOR OPERATING FERROELECTRIC-BASED THREE-DIMENSIONAL FLASH MEMORY INCLUDING DATA STORAGE PATTERN Jan 19, 2023 Pending
Array ( [id] => 18455850 [patent_doc_number] => 20230197131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => ELECTRONIC DEVICE, METHOD FOR CONTROLLING STORING OPERATION, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/067679 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067679 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067679
Electronic device, method for controlling storing operation, and storage medium Dec 15, 2022 Issued
Array ( [id] => 18439692 [patent_doc_number] => 20230186987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SELECTOR RESISTIVE MEMORY, EQUIPPED WITH A CAPACITOR WRITING, AND ASSOCIATED WRITING METHOD [patent_app_type] => utility [patent_app_number] => 18/079325 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18079325 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/079325
Resistive memory with selector, equipped with a write capacitor, and associated writing method Dec 11, 2022 Issued
Array ( [id] => 19773133 [patent_doc_number] => 20250054559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/718810 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18718810 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/718810
SEMICONDUCTOR STORAGE DEVICE AND METHOD Dec 1, 2022 Pending
Array ( [id] => 18255375 [patent_doc_number] => 20230082414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/057386 [patent_app_country] => US [patent_app_date] => 2022-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18057386 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/057386
Nonvolatile memory device and storage device including nonvolatile memory device Nov 20, 2022 Issued
Array ( [id] => 19539245 [patent_doc_number] => 12131800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Physically unclonable cell using dual-interlocking and error correction techniques [patent_app_type] => utility [patent_app_number] => 18/056158 [patent_app_country] => US [patent_app_date] => 2022-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3497 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18056158 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/056158
Physically unclonable cell using dual-interlocking and error correction techniques Nov 15, 2022 Issued
Array ( [id] => 18408680 [patent_doc_number] => 20230170033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => PROGRAM VERIFY PAIRING IN A MULTI-LEVEL CELL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/987780 [patent_app_country] => US [patent_app_date] => 2022-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17987780 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/987780
PROGRAM VERIFY PAIRING IN A MULTI-LEVEL CELL MEMORY DEVICE Nov 14, 2022 Pending
Array ( [id] => 19858041 [patent_doc_number] => 12260891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => MFMFET, MFMFET array, and the operating method thereof [patent_app_type] => utility [patent_app_number] => 17/982156 [patent_app_country] => US [patent_app_date] => 2022-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4630 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982156 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/982156
MFMFET, MFMFET array, and the operating method thereof Nov 6, 2022 Issued
Array ( [id] => 19943436 [patent_doc_number] => 12315572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Managing multi-block operations in memory devices [patent_app_type] => utility [patent_app_number] => 17/981919 [patent_app_country] => US [patent_app_date] => 2022-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13792 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17981919 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/981919
Managing multi-block operations in memory devices Nov 6, 2022 Issued
Array ( [id] => 19918433 [patent_doc_number] => 12293806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Static random-access memory (SRAM) apparatus and method for reducing wire delay [patent_app_type] => utility [patent_app_number] => 18/051142 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1298 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051142 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051142
Static random-access memory (SRAM) apparatus and method for reducing wire delay Oct 30, 2022 Issued
Array ( [id] => 18361045 [patent_doc_number] => 20230142636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => POWER SWITCH CIRCUIT AND NON-VOLATILE MEMORY DEVICE COMPRISING THE SAME [patent_app_type] => utility [patent_app_number] => 18/050489 [patent_app_country] => US [patent_app_date] => 2022-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18050489 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/050489
Power switch circuit and non-volatile memory device comprising the same Oct 27, 2022 Issued
Array ( [id] => 18981837 [patent_doc_number] => 11907009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Phase detection circuit, clock generation circuit and semiconductor apparatus using the phase detection circuit [patent_app_type] => utility [patent_app_number] => 17/975010 [patent_app_country] => US [patent_app_date] => 2022-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 17215 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17975010 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/975010
Phase detection circuit, clock generation circuit and semiconductor apparatus using the phase detection circuit Oct 26, 2022 Issued
Array ( [id] => 18207882 [patent_doc_number] => 20230054139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => STORAGE ARRAY AT LOW LEAKAGE CURRENT [patent_app_type] => utility [patent_app_number] => 18/048854 [patent_app_country] => US [patent_app_date] => 2022-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18048854 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/048854
Storage array having half schmitt inverter Oct 22, 2022 Issued
Array ( [id] => 19926006 [patent_doc_number] => 12300298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Differential storage in memory arrays [patent_app_type] => utility [patent_app_number] => 18/047568 [patent_app_country] => US [patent_app_date] => 2022-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 16152 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047568 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047568
Differential storage in memory arrays Oct 17, 2022 Issued
Array ( [id] => 18183691 [patent_doc_number] => 20230044421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => Memory Power-Gating Techniques [patent_app_type] => utility [patent_app_number] => 17/962828 [patent_app_country] => US [patent_app_date] => 2022-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17962828 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/962828
Memory power-gating techniques Oct 9, 2022 Issued
Array ( [id] => 19100771 [patent_doc_number] => 20240119999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => PHOTONIC CONTENT-ADDRESSABLE MEMORY AND APPLICATIONS THEREOF [patent_app_type] => utility [patent_app_number] => 17/938373 [patent_app_country] => US [patent_app_date] => 2022-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17938373 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/938373
Photonic content-addressable memory and applications thereof Oct 5, 2022 Issued
Array ( [id] => 19085937 [patent_doc_number] => 20240112738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => METHOD OF IMPROVING PROGRAM OPERATION SPEED IN 3D NAND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/937016 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17937016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/937016
Method of improving program operation speed in 3D NAND systems Sep 29, 2022 Issued
Array ( [id] => 19085921 [patent_doc_number] => 20240112722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => DIRECTED REFRESH MANAGEMENT FOR DRAM [patent_app_type] => utility [patent_app_number] => 17/957820 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957820 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/957820
Directed refresh management for DRAM Sep 29, 2022 Issued
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