
Ali Naraghi
Examiner (ID: 17465, Phone: (571)270-5720 , Office: P/2896 )
| Most Active Art Unit | 2896 |
| Art Unit(s) | 2817, 2895, 2896, 2891 |
| Total Applications | 1043 |
| Issued Applications | 867 |
| Pending Applications | 77 |
| Abandoned Applications | 118 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18653110
[patent_doc_number] => 20230298950
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => BOND WIRE LOSS DETECTION AND REDUNDANCY
[patent_app_type] => utility
[patent_app_number] => 17/654847
[patent_app_country] => US
[patent_app_date] => 2022-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6633
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654847
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/654847 | BOND WIRE LOSS DETECTION AND REDUNDANCY | Mar 14, 2022 | Pending |
Array
(
[id] => 19679491
[patent_doc_number] => 12191364
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-07
[patent_title] => Semiconductor device with buried gate structure
[patent_app_type] => utility
[patent_app_number] => 17/689762
[patent_app_country] => US
[patent_app_date] => 2022-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7136
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17689762
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/689762 | Semiconductor device with buried gate structure | Mar 7, 2022 | Issued |
Array
(
[id] => 18258316
[patent_doc_number] => 20230085356
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-16
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/687202
[patent_app_country] => US
[patent_app_date] => 2022-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8375
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17687202
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/687202 | SEMICONDUCTOR DEVICE | Mar 3, 2022 | Pending |
Array
(
[id] => 18615960
[patent_doc_number] => 20230282699
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-07
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/683372
[patent_app_country] => US
[patent_app_date] => 2022-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9399
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683372
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/683372 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Feb 28, 2022 | Pending |
Array
(
[id] => 18600176
[patent_doc_number] => 20230274977
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-31
[patent_title] => Self-Aligned Interconnect Structures and Methods of Forming the Same
[patent_app_type] => utility
[patent_app_number] => 17/681207
[patent_app_country] => US
[patent_app_date] => 2022-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14050
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17681207
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/681207 | Self-Aligned Interconnect Structures and Methods of Forming the Same | Feb 24, 2022 | Pending |
Array
(
[id] => 18379834
[patent_doc_number] => 20230154923
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-18
[patent_title] => DEVICE WITH ALTERNATE COMPLEMENTARY CHANNELS AND FABRICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/677929
[patent_app_country] => US
[patent_app_date] => 2022-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12977
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17677929
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/677929 | DEVICE WITH ALTERNATE COMPLEMENTARY CHANNELS AND FABRICATION METHOD THEREOF | Feb 21, 2022 | Pending |
Array
(
[id] => 19928244
[patent_doc_number] => 12302555
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-13
[patent_title] => Method for forming bit line contact structure and semiconductor structure
[patent_app_type] => utility
[patent_app_number] => 17/676283
[patent_app_country] => US
[patent_app_date] => 2022-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 0
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 265
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676283
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/676283 | Method for forming bit line contact structure and semiconductor structure | Feb 20, 2022 | Issued |
Array
(
[id] => 17963617
[patent_doc_number] => 20220344198
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-27
[patent_title] => Semiconductor Structure and Method for Manufacturing Same
[patent_app_type] => utility
[patent_app_number] => 17/651095
[patent_app_country] => US
[patent_app_date] => 2022-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5443
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17651095
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/651095 | Semiconductor structure and method for manufacturing same | Feb 14, 2022 | Issued |
Array
(
[id] => 19814028
[patent_doc_number] => 12245460
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-04
[patent_title] => Display apparatus
[patent_app_type] => utility
[patent_app_number] => 17/585037
[patent_app_country] => US
[patent_app_date] => 2022-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 19969
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585037
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/585037 | Display apparatus | Jan 25, 2022 | Issued |
Array
(
[id] => 18163995
[patent_doc_number] => 20230030589
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-02
[patent_title] => SEMICONDUCTOR PACKAGE INCLUDING CHIP CONNECTION STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/581194
[patent_app_country] => US
[patent_app_date] => 2022-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10656
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581194
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/581194 | SEMICONDUCTOR PACKAGE INCLUDING CHIP CONNECTION STRUCTURE | Jan 20, 2022 | Pending |
Array
(
[id] => 19048289
[patent_doc_number] => 11937420
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-19
[patent_title] => Memory device having word line with improved adhesion between work function member and conductive layer
[patent_app_type] => utility
[patent_app_number] => 17/578666
[patent_app_country] => US
[patent_app_date] => 2022-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 37
[patent_no_of_words] => 7162
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 281
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578666
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/578666 | Memory device having word line with improved adhesion between work function member and conductive layer | Jan 18, 2022 | Issued |
Array
(
[id] => 18514650
[patent_doc_number] => 20230230910
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-20
[patent_title] => DOUBLE-SIDED REDISTRIBUTION LAYER (RDL) SUBSTRATE FOR PASSIVE AND DEVICE INTEGRATION
[patent_app_type] => utility
[patent_app_number] => 17/579038
[patent_app_country] => US
[patent_app_date] => 2022-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9432
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579038
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/579038 | Double-sided redistribution layer (RDL) substrate for passive and device integration | Jan 18, 2022 | Issued |
Array
(
[id] => 18488542
[patent_doc_number] => 20230215890
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-06
[patent_title] => High Dynamic Range, Backside-illuminated, Low Crosstalk Image Sensor with Walls Between Silicon Surface and First Layer Metal to Isolate Photodiodes
[patent_app_type] => utility
[patent_app_number] => 17/570006
[patent_app_country] => US
[patent_app_date] => 2022-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8876
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570006
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/570006 | High Dynamic Range, Backside-illuminated, Low Crosstalk Image Sensor with Walls Between Silicon Surface and First Layer Metal to Isolate Photodiodes | Jan 5, 2022 | Pending |
Array
(
[id] => 18081174
[patent_doc_number] => 20220406786
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-22
[patent_title] => SEMICONDUCTOR DEVICES HAVING DUMMY GATE STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 17/568262
[patent_app_country] => US
[patent_app_date] => 2022-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9369
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568262
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/568262 | SEMICONDUCTOR DEVICES HAVING DUMMY GATE STRUCTURES | Jan 3, 2022 | Pending |
Array
(
[id] => 20509035
[patent_doc_number] => 12543327
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-03
[patent_title] => On-chip all-solid-state supercapacitor and preparation method thereof
[patent_app_type] => utility
[patent_app_number] => 17/564762
[patent_app_country] => US
[patent_app_date] => 2021-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 0
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 304
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564762
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/564762 | On-chip all-solid-state supercapacitor and preparation method thereof | Dec 28, 2021 | Issued |
Array
(
[id] => 17986383
[patent_doc_number] => 20220352420
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/561056
[patent_app_country] => US
[patent_app_date] => 2021-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15572
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561056
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/561056 | DISPLAY DEVICE | Dec 22, 2021 | Pending |
Array
(
[id] => 17963760
[patent_doc_number] => 20220344341
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-27
[patent_title] => SEMICONDUCTOR DEVICES HAVING AIR GAPS
[patent_app_type] => utility
[patent_app_number] => 17/558855
[patent_app_country] => US
[patent_app_date] => 2021-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9423
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558855
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/558855 | SEMICONDUCTOR DEVICES HAVING AIR GAPS | Dec 21, 2021 | Pending |
Array
(
[id] => 18456341
[patent_doc_number] => 20230197623
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-22
[patent_title] => ELECTRONIC DEVICE INCLUDING AN INTEGRATED CIRCUIT DIE AND A SUPPORT STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/645104
[patent_app_country] => US
[patent_app_date] => 2021-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11220
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17645104
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/645104 | ELECTRONIC DEVICE INCLUDING AN INTEGRATED CIRCUIT DIE AND A SUPPORT STRUCTURE | Dec 19, 2021 | Pending |
Array
(
[id] => 19073429
[patent_doc_number] => 20240107855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-28
[patent_title] => DISPLAY PANEL
[patent_app_type] => utility
[patent_app_number] => 17/621629
[patent_app_country] => US
[patent_app_date] => 2021-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5345
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17621629
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/621629 | DISPLAY PANEL | Dec 9, 2021 | Abandoned |
Array
(
[id] => 18927228
[patent_doc_number] => 20240030232
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-25
[patent_title] => DISPLAY PANEL AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/623214
[patent_app_country] => US
[patent_app_date] => 2021-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4334
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17623214
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/623214 | DISPLAY PANEL AND DISPLAY DEVICE | Dec 8, 2021 | Pending |