
Ali Naraghi
Examiner (ID: 10218, Phone: (571)270-5720 , Office: P/2896 )
| Most Active Art Unit | 2896 |
| Art Unit(s) | 2817, 2891, 2895, 2896 |
| Total Applications | 1024 |
| Issued Applications | 853 |
| Pending Applications | 81 |
| Abandoned Applications | 117 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10477330
[patent_doc_number] => 20150362347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-17
[patent_title] => 'APPARATUS AND METHOD FOR COMPENSATING FOR POSITION ERROR OF RESOLVER'
[patent_app_type] => utility
[patent_app_number] => 14/570294
[patent_app_country] => US
[patent_app_date] => 2014-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2426
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14570294
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/570294 | Apparatus and method for compensating for position error of resolver | Dec 14, 2014 | Issued |
Array
(
[id] => 12376035
[patent_doc_number] => 09960239
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-01
[patent_title] => Electronic device
[patent_app_type] => utility
[patent_app_number] => 15/100689
[patent_app_country] => US
[patent_app_date] => 2014-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 21
[patent_no_of_words] => 5077
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15100689
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/100689 | Electronic device | Dec 6, 2014 | Issued |
Array
(
[id] => 11508712
[patent_doc_number] => 09599867
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-03-21
[patent_title] => 'Display substrate and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 14/559565
[patent_app_country] => US
[patent_app_date] => 2014-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 22
[patent_no_of_words] => 13646
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14559565
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/559565 | Display substrate and method of manufacturing the same | Dec 2, 2014 | Issued |
Array
(
[id] => 13214893
[patent_doc_number] => 10121822
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-11-06
[patent_title] => Light-emitting device and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 15/100748
[patent_app_country] => US
[patent_app_date] => 2014-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 9888
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15100748
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/100748 | Light-emitting device and method of forming the same | Nov 17, 2014 | Issued |
Array
(
[id] => 10795197
[patent_doc_number] => 20160141354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-19
[patent_title] => 'Patterned Back-Barrier for III-Nitride Semiconductor Devices'
[patent_app_type] => utility
[patent_app_number] => 14/540463
[patent_app_country] => US
[patent_app_date] => 2014-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4029
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14540463
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/540463 | Patterned back-barrier for III-nitride semiconductor devices | Nov 12, 2014 | Issued |
Array
(
[id] => 10309439
[patent_doc_number] => 20150194440
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-09
[patent_title] => 'Nonvolatile Memory Devices And Methods Of Fabricating The Same'
[patent_app_type] => utility
[patent_app_number] => 14/539043
[patent_app_country] => US
[patent_app_date] => 2014-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 12725
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14539043
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/539043 | Nonvolatile memory devices and methods of fabricating the same | Nov 11, 2014 | Issued |
Array
(
[id] => 10343583
[patent_doc_number] => 20150228588
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-13
[patent_title] => 'Semiconductor Wafers Including Indications of Crystal Orientation and Methods of Forming the Same'
[patent_app_type] => utility
[patent_app_number] => 14/519788
[patent_app_country] => US
[patent_app_date] => 2014-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 7962
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14519788
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/519788 | Semiconductor wafers including indications of crystal orientation and methods of forming the same | Oct 20, 2014 | Issued |
Array
(
[id] => 10725659
[patent_doc_number] => 20160071807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-10
[patent_title] => 'METHODOLOGY TO ACHIEVE ZERO WARPAGE FOR IC PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 14/518887
[patent_app_country] => US
[patent_app_date] => 2014-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5253
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518887
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/518887 | Methodology to achieve zero warpage for IC package | Oct 19, 2014 | Issued |
Array
(
[id] => 10765209
[patent_doc_number] => 20160111366
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-04-21
[patent_title] => 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/518050
[patent_app_country] => US
[patent_app_date] => 2014-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4930
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14518050
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/518050 | Semiconductor structure and manufacturing method of the same | Oct 19, 2014 | Issued |
Array
(
[id] => 11524666
[patent_doc_number] => 09608078
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-03-28
[patent_title] => 'Semiconductor device with improved field plate'
[patent_app_type] => utility
[patent_app_number] => 14/517285
[patent_app_country] => US
[patent_app_date] => 2014-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 7433
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517285
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/517285 | Semiconductor device with improved field plate | Oct 16, 2014 | Issued |
Array
(
[id] => 11687282
[patent_doc_number] => 09685332
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-20
[patent_title] => 'Iterative self-aligned patterning'
[patent_app_type] => utility
[patent_app_number] => 14/517252
[patent_app_country] => US
[patent_app_date] => 2014-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 4866
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517252
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/517252 | Iterative self-aligned patterning | Oct 16, 2014 | Issued |
Array
(
[id] => 12335388
[patent_doc_number] => 09947797
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-17
[patent_title] => Semiconductor device and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 14/496368
[patent_app_country] => US
[patent_app_date] => 2014-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 60
[patent_no_of_words] => 27439
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14496368
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/496368 | Semiconductor device and method for manufacturing the same | Sep 24, 2014 | Issued |
Array
(
[id] => 9875118
[patent_doc_number] => 08962385
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-02-24
[patent_title] => 'ReRAM device structure'
[patent_app_type] => utility
[patent_app_number] => 14/490062
[patent_app_country] => US
[patent_app_date] => 2014-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3216
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14490062
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/490062 | ReRAM device structure | Sep 17, 2014 | Issued |
Array
(
[id] => 10800966
[patent_doc_number] => 20160147123
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-26
[patent_title] => 'ARRAY SUBSTRATE AND DISPLAY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/435923
[patent_app_country] => US
[patent_app_date] => 2014-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4110
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14435923
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/435923 | Array substrate and display device | Sep 17, 2014 | Issued |
Array
(
[id] => 9789660
[patent_doc_number] => 20150001605
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-01
[patent_title] => 'Gate Constructions Of Recessed Access Devices And Methods Of Forming Gate Constructions Of Recessed Access Devices'
[patent_app_type] => utility
[patent_app_number] => 14/487201
[patent_app_country] => US
[patent_app_date] => 2014-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 3970
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487201
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/487201 | Gate Constructions Of Recessed Access Devices And Methods Of Forming Gate Constructions Of Recessed Access Devices | Sep 15, 2014 | Abandoned |
Array
(
[id] => 11360172
[patent_doc_number] => 09536829
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-01-03
[patent_title] => 'Programmable electrical fuse in keep out zone'
[patent_app_type] => utility
[patent_app_number] => 14/483258
[patent_app_country] => US
[patent_app_date] => 2014-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 6246
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483258
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/483258 | Programmable electrical fuse in keep out zone | Sep 10, 2014 | Issued |
Array
(
[id] => 10402719
[patent_doc_number] => 20150287729
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-08
[patent_title] => 'SEMICONDUCTOR DEVICE LAYOUT AND METHOD FOR FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/483063
[patent_app_country] => US
[patent_app_date] => 2014-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3155
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483063
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/483063 | Semiconductor device layout and method for forming the same | Sep 9, 2014 | Issued |
Array
(
[id] => 12040509
[patent_doc_number] => 09818744
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-14
[patent_title] => 'Leakage current suppression methods and related structures'
[patent_app_type] => utility
[patent_app_number] => 14/477491
[patent_app_country] => US
[patent_app_date] => 2014-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 38
[patent_no_of_words] => 11175
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477491
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/477491 | Leakage current suppression methods and related structures | Sep 3, 2014 | Issued |
Array
(
[id] => 10351009
[patent_doc_number] => 20150236014
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-20
[patent_title] => 'STACKED METAL OXIDE SEMICONDUCTOR (MOS) AND METAL OXIDE METAL (MOM) CAPACITOR ARCHITECTURE'
[patent_app_type] => utility
[patent_app_number] => 14/476086
[patent_app_country] => US
[patent_app_date] => 2014-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8392
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14476086
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/476086 | Stacked metal oxide semiconductor (MOS) and metal oxide metal (MOM) capacitor architecture | Sep 2, 2014 | Issued |
Array
(
[id] => 10718338
[patent_doc_number] => 20160064484
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-03
[patent_title] => 'LATERAL BIPOLAR JUNCTION TRANSISTORS ON A SILICON-ON-INSULATOR SUBSTRATE WITH A THIN DEVICE LAYER THICKNESS'
[patent_app_type] => utility
[patent_app_number] => 14/476007
[patent_app_country] => US
[patent_app_date] => 2014-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5604
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14476007
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/476007 | Lateral bipolar junction transistors on a silicon-on-insulator substrate with a thin device layer thickness | Sep 2, 2014 | Issued |