Search

Ali Naraghi

Examiner (ID: 10218, Phone: (571)270-5720 , Office: P/2896 )

Most Active Art Unit
2896
Art Unit(s)
2817, 2891, 2895, 2896
Total Applications
1024
Issued Applications
853
Pending Applications
81
Abandoned Applications
117

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7570885 [patent_doc_number] => 20110266541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'Probe Pad On A Corner Stress Relief Region In A Semiconductor Chip' [patent_app_type] => utility [patent_app_number] => 13/180304 [patent_app_country] => US [patent_app_date] => 2011-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20110266541.pdf [firstpage_image] =>[orig_patent_app_number] => 13180304 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/180304
Probe pad on a corner stress relief region in a semiconductor chip Jul 10, 2011 Issued
Array ( [id] => 8469754 [patent_doc_number] => 08298932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Vertical interconnect structure, memory device and associated production method' [patent_app_type] => utility [patent_app_number] => 13/167744 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 6095 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167744 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167744
Vertical interconnect structure, memory device and associated production method Jun 23, 2011 Issued
Array ( [id] => 8469754 [patent_doc_number] => 08298932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Vertical interconnect structure, memory device and associated production method' [patent_app_type] => utility [patent_app_number] => 13/167744 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 6095 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167744 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167744
Vertical interconnect structure, memory device and associated production method Jun 23, 2011 Issued
Array ( [id] => 8469754 [patent_doc_number] => 08298932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Vertical interconnect structure, memory device and associated production method' [patent_app_type] => utility [patent_app_number] => 13/167744 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 6095 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167744 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167744
Vertical interconnect structure, memory device and associated production method Jun 23, 2011 Issued
Array ( [id] => 8469754 [patent_doc_number] => 08298932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Vertical interconnect structure, memory device and associated production method' [patent_app_type] => utility [patent_app_number] => 13/167744 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 6095 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167744 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167744
Vertical interconnect structure, memory device and associated production method Jun 23, 2011 Issued
Array ( [id] => 9113667 [patent_doc_number] => 08569846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'MOS devices with improved source/drain regions with SiGe' [patent_app_type] => utility [patent_app_number] => 13/166481 [patent_app_country] => US [patent_app_date] => 2011-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2796 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13166481 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/166481
MOS devices with improved source/drain regions with SiGe Jun 21, 2011 Issued
Array ( [id] => 9113667 [patent_doc_number] => 08569846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'MOS devices with improved source/drain regions with SiGe' [patent_app_type] => utility [patent_app_number] => 13/166481 [patent_app_country] => US [patent_app_date] => 2011-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2796 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13166481 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/166481
MOS devices with improved source/drain regions with SiGe Jun 21, 2011 Issued
Array ( [id] => 7775407 [patent_doc_number] => 08120057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Semiconductor light emitting element' [patent_app_type] => utility [patent_app_number] => 13/155045 [patent_app_country] => US [patent_app_date] => 2011-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 25275 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120057.pdf [firstpage_image] =>[orig_patent_app_number] => 13155045 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/155045
Semiconductor light emitting element Jun 6, 2011 Issued
Array ( [id] => 6161289 [patent_doc_number] => 20110193169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'Techniques for Three-Dimensional Circuit Integration' [patent_app_type] => utility [patent_app_number] => 13/088339 [patent_app_country] => US [patent_app_date] => 2011-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7089 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20110193169.pdf [firstpage_image] =>[orig_patent_app_number] => 13088339 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/088339
Techniques for three-dimensional circuit integration Apr 15, 2011 Issued
Array ( [id] => 9140882 [patent_doc_number] => 08581345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Charge-balance power device comprising columnar structures and having reduced resistance, and method and system of same' [patent_app_type] => utility [patent_app_number] => 13/083012 [patent_app_country] => US [patent_app_date] => 2011-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 5752 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13083012 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/083012
Charge-balance power device comprising columnar structures and having reduced resistance, and method and system of same Apr 7, 2011 Issued
Array ( [id] => 9239801 [patent_doc_number] => 08604596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Integrated circuit packaging system with locking interconnects and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 13/071433 [patent_app_country] => US [patent_app_date] => 2011-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4673 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13071433 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/071433
Integrated circuit packaging system with locking interconnects and method of manufacture thereof Mar 23, 2011 Issued
Array ( [id] => 7480166 [patent_doc_number] => 20110248408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'Package substrate and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 13/064437 [patent_app_country] => US [patent_app_date] => 2011-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2566 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248408.pdf [firstpage_image] =>[orig_patent_app_number] => 13064437 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/064437
Package substrate and fabricating method thereof Mar 23, 2011 Abandoned
Array ( [id] => 7490337 [patent_doc_number] => 08030137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Flexible interposer for stacking semiconductor chips and connecting same to substrate' [patent_app_type] => utility [patent_app_number] => 13/048112 [patent_app_country] => US [patent_app_date] => 2011-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3416 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030137.pdf [firstpage_image] =>[orig_patent_app_number] => 13048112 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/048112
Flexible interposer for stacking semiconductor chips and connecting same to substrate Mar 14, 2011 Issued
Array ( [id] => 9576018 [patent_doc_number] => 08766436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Moisture barrier for a wire bond' [patent_app_type] => utility [patent_app_number] => 13/037836 [patent_app_country] => US [patent_app_date] => 2011-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2393 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13037836 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/037836
Moisture barrier for a wire bond Feb 28, 2011 Issued
Array ( [id] => 5959105 [patent_doc_number] => 20110183492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'Methods of forming oxides, methods of forming semiconductor constructions, and methods of forming isolation regions' [patent_app_type] => utility [patent_app_number] => 13/031584 [patent_app_country] => US [patent_app_date] => 2011-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4001 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20110183492.pdf [firstpage_image] =>[orig_patent_app_number] => 13031584 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/031584
Methods of forming oxides, methods of forming semiconductor constructions, and methods of forming isolation regions Feb 20, 2011 Issued
Array ( [id] => 9086250 [patent_doc_number] => 08557677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Stack-type semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/120792 [patent_app_country] => US [patent_app_date] => 2011-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3988 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13120792 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/120792
Stack-type semiconductor device and method for manufacturing the same Feb 16, 2011 Issued
Array ( [id] => 7811252 [patent_doc_number] => 08133782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Nonvolatile semiconductor memory device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 13/028730 [patent_app_country] => US [patent_app_date] => 2011-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 35 [patent_no_of_words] => 6850 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/133/08133782.pdf [firstpage_image] =>[orig_patent_app_number] => 13028730 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/028730
Nonvolatile semiconductor memory device and manufacturing method thereof Feb 15, 2011 Issued
Array ( [id] => 8706041 [patent_doc_number] => 20130063329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/695217 [patent_app_country] => US [patent_app_date] => 2011-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15967 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13695217 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/695217
Semiconductor device, display device, and method for manufacturing semiconductor device Feb 9, 2011 Issued
Array ( [id] => 6169917 [patent_doc_number] => 20110175162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/009182 [patent_app_country] => US [patent_app_date] => 2011-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4205 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20110175162.pdf [firstpage_image] =>[orig_patent_app_number] => 13009182 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/009182
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME Jan 18, 2011 Abandoned
Array ( [id] => 9428249 [patent_doc_number] => 08704329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-22 [patent_title] => 'SOI devices for plasma display panel driver chip' [patent_app_type] => utility [patent_app_number] => 13/503684 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8668 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13503684 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/503684
SOI devices for plasma display panel driver chip Dec 28, 2010 Issued
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