Search

Alice W. Tang

Examiner (ID: 5661)

Most Active Art Unit
2503
Art Unit(s)
2503, 2814, 2815
Total Applications
308
Issued Applications
136
Pending Applications
67
Abandoned Applications
109

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3757628 [patent_doc_number] => 05721196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Stacked tunneling and stepped grain boundary Josephson junction' [patent_app_type] => 1 [patent_app_number] => 8/698763 [patent_app_country] => US [patent_app_date] => 1996-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 5031 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721196.pdf [firstpage_image] =>[orig_patent_app_number] => 698763 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/698763
Stacked tunneling and stepped grain boundary Josephson junction Aug 15, 1996 Issued
Array ( [id] => 3799595 [patent_doc_number] => 05780910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'SRAM with stacked capacitor spaced from gate electrodes' [patent_app_type] => 1 [patent_app_number] => 8/682243 [patent_app_country] => US [patent_app_date] => 1996-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 71 [patent_no_of_words] => 19065 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780910.pdf [firstpage_image] =>[orig_patent_app_number] => 682243 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/682243
SRAM with stacked capacitor spaced from gate electrodes Jul 16, 1996 Issued
Array ( [id] => 3802149 [patent_doc_number] => 05828121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Multi-level conduction structure for VLSI circuits' [patent_app_type] => 1 [patent_app_number] => 8/668518 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2075 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828121.pdf [firstpage_image] =>[orig_patent_app_number] => 668518 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668518
Multi-level conduction structure for VLSI circuits Jun 26, 1996 Issued
Array ( [id] => 3882932 [patent_doc_number] => 05804877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Low-resistance contact on a compound semiconductor' [patent_app_type] => 1 [patent_app_number] => 8/667318 [patent_app_country] => US [patent_app_date] => 1996-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 5239 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/804/05804877.pdf [firstpage_image] =>[orig_patent_app_number] => 667318 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/667318
Low-resistance contact on a compound semiconductor Jun 19, 1996 Issued
Array ( [id] => 3865211 [patent_doc_number] => 05793114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Self-aligned method for forming contact with zero offset to gate' [patent_app_type] => 1 [patent_app_number] => 8/639316 [patent_app_country] => US [patent_app_date] => 1996-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3186 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793114.pdf [firstpage_image] =>[orig_patent_app_number] => 639316 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/639316
Self-aligned method for forming contact with zero offset to gate Apr 23, 1996 Issued
Array ( [id] => 3895800 [patent_doc_number] => 05834800 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Heterojunction bipolar transistor having mono crystalline SiGe intrinsic base and polycrystalline SiGe and Si extrinsic base regions' [patent_app_type] => 1 [patent_app_number] => 8/610026 [patent_app_country] => US [patent_app_date] => 1996-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 4260 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834800.pdf [firstpage_image] =>[orig_patent_app_number] => 610026 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/610026
Heterojunction bipolar transistor having mono crystalline SiGe intrinsic base and polycrystalline SiGe and Si extrinsic base regions Mar 3, 1996 Issued
Array ( [id] => 3857305 [patent_doc_number] => 05767540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Hetero-junction bipolar transistor having AlGaAsP emitter layer underneath a base electrode' [patent_app_type] => 1 [patent_app_number] => 8/605539 [patent_app_country] => US [patent_app_date] => 1996-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5795 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767540.pdf [firstpage_image] =>[orig_patent_app_number] => 605539 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/605539
Hetero-junction bipolar transistor having AlGaAsP emitter layer underneath a base electrode Feb 21, 1996 Issued
Array ( [id] => 3834750 [patent_doc_number] => 05760463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Superconducting layer in contact with group III-V semiconductor layer for wiring structure' [patent_app_type] => 1 [patent_app_number] => 8/601646 [patent_app_country] => US [patent_app_date] => 1996-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4816 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/760/05760463.pdf [firstpage_image] =>[orig_patent_app_number] => 601646 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/601646
Superconducting layer in contact with group III-V semiconductor layer for wiring structure Feb 13, 1996 Issued
08/591105 SEMICONDUCTOR MEMORY AND METHOD OF FABRICATING THE SAME Jan 24, 1996 Abandoned
08/575079 FIELD EFFECT TRANSISTOR Dec 18, 1995 Abandoned
Array ( [id] => 3534072 [patent_doc_number] => 05583353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Heterojunction field effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/590107 [patent_app_country] => US [patent_app_date] => 1995-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2221 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583353.pdf [firstpage_image] =>[orig_patent_app_number] => 590107 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/590107
Heterojunction field effect transistor Nov 5, 1995 Issued
Array ( [id] => 3817979 [patent_doc_number] => 05710441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Microcavity LED with photon recycling' [patent_app_type] => 1 [patent_app_number] => 8/550147 [patent_app_country] => US [patent_app_date] => 1995-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2177 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710441.pdf [firstpage_image] =>[orig_patent_app_number] => 550147 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/550147
Microcavity LED with photon recycling Oct 29, 1995 Issued
Array ( [id] => 3790755 [patent_doc_number] => 05736755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Vertical PNP power device with different ballastic resistant vertical PNP transistors' [patent_app_type] => 1 [patent_app_number] => 8/525894 [patent_app_country] => US [patent_app_date] => 1995-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1206 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/736/05736755.pdf [firstpage_image] =>[orig_patent_app_number] => 525894 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/525894
Vertical PNP power device with different ballastic resistant vertical PNP transistors Sep 7, 1995 Issued
08/483047 A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE Jun 6, 1995 Abandoned
Array ( [id] => 3705863 [patent_doc_number] => 05654259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Superconductive conjugate photoconductive substances of the Bi-SrCa (laY)-Cu-O system, a method for producing the same and superconductive optoelectronic devices using the same' [patent_app_type] => 1 [patent_app_number] => 8/473905 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 8226 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654259.pdf [firstpage_image] =>[orig_patent_app_number] => 473905 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/473905
Superconductive conjugate photoconductive substances of the Bi-SrCa (laY)-Cu-O system, a method for producing the same and superconductive optoelectronic devices using the same Jun 6, 1995 Issued
Array ( [id] => 3553311 [patent_doc_number] => 05548132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions' [patent_app_type] => 1 [patent_app_number] => 8/484979 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3742 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548132.pdf [firstpage_image] =>[orig_patent_app_number] => 484979 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/484979
Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions Jun 6, 1995 Issued
Array ( [id] => 3579864 [patent_doc_number] => 05523615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Porous dielectric material with improved pore surface properties for electronics applications' [patent_app_type] => 1 [patent_app_number] => 8/474273 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3539 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/523/05523615.pdf [firstpage_image] =>[orig_patent_app_number] => 474273 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/474273
Porous dielectric material with improved pore surface properties for electronics applications Jun 6, 1995 Issued
Array ( [id] => 3766106 [patent_doc_number] => 05844250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Field emission element with single crystalline or preferred oriented polycrystalline emitter or insulating layer' [patent_app_type] => 1 [patent_app_number] => 8/483853 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 42 [patent_no_of_words] => 9371 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844250.pdf [firstpage_image] =>[orig_patent_app_number] => 483853 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/483853
Field emission element with single crystalline or preferred oriented polycrystalline emitter or insulating layer Jun 6, 1995 Issued
08/478472 NONVOLATILE MEMORY DEVICE Jun 6, 1995 Abandoned
Array ( [id] => 3496317 [patent_doc_number] => 05561318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Porous composites as a low dielectric constant material for electronics applications' [patent_app_type] => 1 [patent_app_number] => 8/477029 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 4764 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561318.pdf [firstpage_image] =>[orig_patent_app_number] => 477029 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/477029
Porous composites as a low dielectric constant material for electronics applications Jun 6, 1995 Issued
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