
Alicia Ann Chevalier
Supervisory Patent Examiner (ID: 9126, Phone: (571)272-1490 , Office: P/1788 )
| Most Active Art Unit | 1772 |
| Art Unit(s) | 1772, 1788, 1794, 1783 |
| Total Applications | 593 |
| Issued Applications | 202 |
| Pending Applications | 40 |
| Abandoned Applications | 352 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3702146
[patent_doc_number] => 05664205
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'Power management control technique for timer tick activity within an interrupt driven computer system'
[patent_app_type] => 1
[patent_app_number] => 8/700129
[patent_app_country] => US
[patent_app_date] => 1996-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 3590
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/664/05664205.pdf
[firstpage_image] =>[orig_patent_app_number] => 700129
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/700129 | Power management control technique for timer tick activity within an interrupt driven computer system | Aug 19, 1996 | Issued |
Array
(
[id] => 3716207
[patent_doc_number] => 05675747
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-07
[patent_title] => 'Data transmission system with erroneous connection indicator'
[patent_app_type] => 1
[patent_app_number] => 8/699691
[patent_app_country] => US
[patent_app_date] => 1996-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2523
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/675/05675747.pdf
[firstpage_image] =>[orig_patent_app_number] => 699691
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/699691 | Data transmission system with erroneous connection indicator | Aug 14, 1996 | Issued |
Array
(
[id] => 3734108
[patent_doc_number] => 05682485
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-28
[patent_title] => 'Deadlock avoidance for switched interconnect bus systems'
[patent_app_type] => 1
[patent_app_number] => 8/692988
[patent_app_country] => US
[patent_app_date] => 1996-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3828
[patent_no_of_claims] => 13
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[pdf_file] => patents/05/682/05682485.pdf
[firstpage_image] =>[orig_patent_app_number] => 692988
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/692988 | Deadlock avoidance for switched interconnect bus systems | Aug 6, 1996 | Issued |
Array
(
[id] => 3672737
[patent_doc_number] => 05649121
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'Method and apparatus for providing a remotely located outrigger card electrically coupled to a control card'
[patent_app_type] => 1
[patent_app_number] => 8/674614
[patent_app_country] => US
[patent_app_date] => 1996-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 4257
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 290
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[pdf_file] => patents/05/649/05649121.pdf
[firstpage_image] =>[orig_patent_app_number] => 674614
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/674614 | Method and apparatus for providing a remotely located outrigger card electrically coupled to a control card | Jun 27, 1996 | Issued |
Array
(
[id] => 3674112
[patent_doc_number] => 05649213
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'Method and apparatus for reducing power consumption in a computer system'
[patent_app_type] => 1
[patent_app_number] => 8/636010
[patent_app_country] => US
[patent_app_date] => 1996-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 5664
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[pdf_file] => patents/05/649/05649213.pdf
[firstpage_image] =>[orig_patent_app_number] => 636010
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/636010 | Method and apparatus for reducing power consumption in a computer system | Apr 21, 1996 | Issued |
Array
(
[id] => 3709111
[patent_doc_number] => 05619707
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-08
[patent_title] => 'Video subsystem power management apparatus and method'
[patent_app_type] => 1
[patent_app_number] => 8/630540
[patent_app_country] => US
[patent_app_date] => 1996-04-10
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[pdf_file] => patents/05/619/05619707.pdf
[firstpage_image] =>[orig_patent_app_number] => 630540
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/630540 | Video subsystem power management apparatus and method | Apr 9, 1996 | Issued |
Array
(
[id] => 3744987
[patent_doc_number] => 05694555
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Method and apparatus for exchanging data, status, and commands over an hierarchical serial bus assembly using communication packets'
[patent_app_type] => 1
[patent_app_number] => 8/619863
[patent_app_country] => US
[patent_app_date] => 1996-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 40
[patent_no_of_words] => 8446
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[pdf_file] => patents/05/694/05694555.pdf
[firstpage_image] =>[orig_patent_app_number] => 619863
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/619863 | Method and apparatus for exchanging data, status, and commands over an hierarchical serial bus assembly using communication packets | Mar 18, 1996 | Issued |
Array
(
[id] => 3660791
[patent_doc_number] => 05630148
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-13
[patent_title] => 'Dynamic processor performance and power management in a computer system'
[patent_app_type] => 1
[patent_app_number] => 8/613778
[patent_app_country] => US
[patent_app_date] => 1996-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3639
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[pdf_file] => patents/05/630/05630148.pdf
[firstpage_image] =>[orig_patent_app_number] => 613778
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/613778 | Dynamic processor performance and power management in a computer system | Feb 27, 1996 | Issued |
Array
(
[id] => 3744167
[patent_doc_number] => 05666540
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-09
[patent_title] => 'Information processing system'
[patent_app_type] => 1
[patent_app_number] => 8/600322
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[firstpage_image] =>[orig_patent_app_number] => 600322
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/600322 | Information processing system | Feb 12, 1996 | Issued |
Array
(
[id] => 3738219
[patent_doc_number] => 05652845
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[patent_kind] => NA
[patent_issue_date] => 1997-07-29
[patent_title] => 'Display apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/598903
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[patent_app_date] => 1996-02-09
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/652/05652845.pdf
[firstpage_image] =>[orig_patent_app_number] => 598903
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/598903 | Display apparatus | Feb 8, 1996 | Issued |
Array
(
[id] => 3595377
[patent_doc_number] => 05585740
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-17
[patent_title] => 'CMOS low output voltage bus driver with controlled clamps'
[patent_app_type] => 1
[patent_app_number] => 8/597475
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[pdf_file] => patents/05/585/05585740.pdf
[firstpage_image] =>[orig_patent_app_number] => 597475
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/597475 | CMOS low output voltage bus driver with controlled clamps | Feb 1, 1996 | Issued |
Array
(
[id] => 3635257
[patent_doc_number] => 05613075
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-18
[patent_title] => 'Method and apparatus for providing deterministic read access to main memory in a computer system'
[patent_app_type] => 1
[patent_app_number] => 8/585598
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[firstpage_image] =>[orig_patent_app_number] => 585598
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/585598 | Method and apparatus for providing deterministic read access to main memory in a computer system | Jan 11, 1996 | Issued |
Array
(
[id] => 3730446
[patent_doc_number] => 05617546
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-01
[patent_title] => 'Data bus architecture compatible with 32-bit and 64-bit processors'
[patent_app_type] => 1
[patent_app_number] => 8/584705
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/584705 | Data bus architecture compatible with 32-bit and 64-bit processors | Jan 10, 1996 | Issued |
Array
(
[id] => 3674098
[patent_doc_number] => 05649212
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'Information processing system having a floppy disk drive with disk protection during a resume mode'
[patent_app_type] => 1
[patent_app_number] => 8/584994
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[firstpage_image] =>[orig_patent_app_number] => 584994
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/584994 | Information processing system having a floppy disk drive with disk protection during a resume mode | Jan 10, 1996 | Issued |
Array
(
[id] => 3642641
[patent_doc_number] => 05687379
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[patent_issue_date] => 1997-11-11
[patent_title] => 'Method and apparatus for preventing unauthorized access to peripheral devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/583277 | Method and apparatus for preventing unauthorized access to peripheral devices | Jan 4, 1996 | Issued |
Array
(
[id] => 3647546
[patent_doc_number] => 05611054
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[patent_issue_date] => 1997-03-11
[patent_title] => 'Method and apparatus for decoding and recoding of addresses'
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[pdf_file] => patents/05/611/05611054.pdf
[firstpage_image] =>[orig_patent_app_number] => 567405
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/567405 | Method and apparatus for decoding and recoding of addresses | Dec 4, 1995 | Issued |
Array
(
[id] => 3741741
[patent_doc_number] => 05671387
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[patent_issue_date] => 1997-09-23
[patent_title] => 'Method of automatically assigning device addresses to devices communicating over a common data bus'
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Array
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[id] => 3641878
[patent_doc_number] => 05687326
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[firstpage_image] =>[orig_patent_app_number] => 545881
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/545881 | Methods and apparatus for implementing a high speed serial link and serial data bus | Oct 19, 1995 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/543764 | Method and apparatus for spurious interrupt detection in a data processing system | Oct 15, 1995 | Issued |
Array
(
[id] => 3701628
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[pdf_file] => patents/05/604/05604871.pdf
[firstpage_image] =>[orig_patent_app_number] => 540975
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/540975 | Modular host local expansion upgrade | Oct 10, 1995 | Issued |