| Application number | Title of the application | Filing Date | Status |
|---|
| 08/350380 | FLEXIBLE USER INTERFACE CIRCUIT IN A MEMORY DEVICE | Dec 4, 1994 | Abandoned |
Array
(
[id] => 3674042
[patent_doc_number] => 05649207
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'Microprocessor unit having interrupt mechanism'
[patent_app_type] => 1
[patent_app_number] => 8/348373
[patent_app_country] => US
[patent_app_date] => 1994-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2238
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/649/05649207.pdf
[firstpage_image] =>[orig_patent_app_number] => 348373
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/348373 | Microprocessor unit having interrupt mechanism | Nov 30, 1994 | Issued |
| 08/347669 | DEADLOCK AVOIDANCE FOR SWITCHED INTERCONNECT BUS SYSTEMS | Nov 30, 1994 | Abandoned |
Array
(
[id] => 3601729
[patent_doc_number] => 05551044
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-27
[patent_title] => 'Method and apparatus for interrupt/SMI# ordering'
[patent_app_type] => 1
[patent_app_number] => 8/349065
[patent_app_country] => US
[patent_app_date] => 1994-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 9629
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/551/05551044.pdf
[firstpage_image] =>[orig_patent_app_number] => 349065
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/349065 | Method and apparatus for interrupt/SMI# ordering | Nov 30, 1994 | Issued |
Array
(
[id] => 3540014
[patent_doc_number] => 05542053
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Bridge interface between two buses of a computer system with a direct memory access controller programmed by a scatter/gather programmer'
[patent_app_type] => 1
[patent_app_number] => 8/350184
[patent_app_country] => US
[patent_app_date] => 1994-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 8438
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/542/05542053.pdf
[firstpage_image] =>[orig_patent_app_number] => 350184
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/350184 | Bridge interface between two buses of a computer system with a direct memory access controller programmed by a scatter/gather programmer | Nov 29, 1994 | Issued |
Array
(
[id] => 3621822
[patent_doc_number] => 05590342
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-31
[patent_title] => 'Method and apparatus for reducing power consumption in a computer system using virtual device drivers'
[patent_app_type] => 1
[patent_app_number] => 8/346040
[patent_app_country] => US
[patent_app_date] => 1994-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6239
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/590/05590342.pdf
[firstpage_image] =>[orig_patent_app_number] => 346040
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/346040 | Method and apparatus for reducing power consumption in a computer system using virtual device drivers | Nov 28, 1994 | Issued |
| 08/339455 | METHOD AND APPARATUS FOR PROVIDING A REMOTELY LOCATED OUTRIGGER CARD ELECTRICALLY COUPLED TO A CONTROL CARD | Nov 13, 1994 | Abandoned |
| 08/332573 | METHOD AND APPARATUS FOR EXCHANGING DATA, STATUS AND COMMANDS OVER AN HIERARCHICAL SERIAL BUSS ASSEMBLY USING COMMUNICATION PACKETS | Oct 30, 1994 | Abandoned |
Array
(
[id] => 3566811
[patent_doc_number] => 05574920
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'Method for controlling power down of a hard disk drive in a computer'
[patent_app_type] => 1
[patent_app_number] => 8/328366
[patent_app_country] => US
[patent_app_date] => 1994-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7758
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/574/05574920.pdf
[firstpage_image] =>[orig_patent_app_number] => 328366
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/328366 | Method for controlling power down of a hard disk drive in a computer | Oct 24, 1994 | Issued |
Array
(
[id] => 3670725
[patent_doc_number] => 05659761
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-19
[patent_title] => 'Data recognition apparatus and portable data reader having power management system'
[patent_app_type] => 1
[patent_app_number] => 8/324980
[patent_app_country] => US
[patent_app_date] => 1994-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 8818
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/659/05659761.pdf
[firstpage_image] =>[orig_patent_app_number] => 324980
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/324980 | Data recognition apparatus and portable data reader having power management system | Oct 17, 1994 | Issued |
Array
(
[id] => 3701450
[patent_doc_number] => 05644782
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-01
[patent_title] => 'System with virtual update capable read-only memory'
[patent_app_type] => 1
[patent_app_number] => 8/323564
[patent_app_country] => US
[patent_app_date] => 1994-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2007
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/644/05644782.pdf
[firstpage_image] =>[orig_patent_app_number] => 323564
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/323564 | System with virtual update capable read-only memory | Oct 16, 1994 | Issued |
Array
(
[id] => 3738956
[patent_doc_number] => 05652892
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-29
[patent_title] => 'Method and apparatus for controlling remote power source'
[patent_app_type] => 1
[patent_app_number] => 8/323886
[patent_app_country] => US
[patent_app_date] => 1994-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 3790
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/652/05652892.pdf
[firstpage_image] =>[orig_patent_app_number] => 323886
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/323886 | Method and apparatus for controlling remote power source | Oct 16, 1994 | Issued |
Array
(
[id] => 3505432
[patent_doc_number] => 05537558
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-16
[patent_title] => 'Apparatus and method for communicating multiple devices through one PCMCIA interface'
[patent_app_type] => 1
[patent_app_number] => 8/321057
[patent_app_country] => US
[patent_app_date] => 1994-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5397
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/537/05537558.pdf
[firstpage_image] =>[orig_patent_app_number] => 321057
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/321057 | Apparatus and method for communicating multiple devices through one PCMCIA interface | Oct 4, 1994 | Issued |
| 08/318052 | METHOD AND APPARATUS FOR MANAGING POWER CONSUMPTION OF PERIPHERAL DEVICES OF PERSONAL COMPUTERS | Oct 3, 1994 | Abandoned |
Array
(
[id] => 3701100
[patent_doc_number] => 05664135
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'Apparatus and method for reducing delays due to branches'
[patent_app_type] => 1
[patent_app_number] => 8/313980
[patent_app_country] => US
[patent_app_date] => 1994-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5046
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/664/05664135.pdf
[firstpage_image] =>[orig_patent_app_number] => 313980
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/313980 | Apparatus and method for reducing delays due to branches | Sep 27, 1994 | Issued |
Array
(
[id] => 3562157
[patent_doc_number] => 05548730
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Intelligent bus bridge for input/output subsystems in a computer system'
[patent_app_type] => 1
[patent_app_number] => 8/309106
[patent_app_country] => US
[patent_app_date] => 1994-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4802
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/548/05548730.pdf
[firstpage_image] =>[orig_patent_app_number] => 309106
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/309106 | Intelligent bus bridge for input/output subsystems in a computer system | Sep 19, 1994 | Issued |
| 08/308166 | METHOD AND APPARATUS FOR PROVIDING REGISTER ANFD INTERRUPT COMPATIBILITY BETWEEN NON-IDENTICAL INTEGRATED CIRCUITS | Sep 15, 1994 | Abandoned |
Array
(
[id] => 3887592
[patent_doc_number] => 05838933
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Control circuit and method for a first-in first-out data pipeline'
[patent_app_type] => 1
[patent_app_number] => 8/303919
[patent_app_country] => US
[patent_app_date] => 1994-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 6102
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/838/05838933.pdf
[firstpage_image] =>[orig_patent_app_number] => 303919
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/303919 | Control circuit and method for a first-in first-out data pipeline | Sep 8, 1994 | Issued |
Array
(
[id] => 3674254
[patent_doc_number] => 05657455
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Status indicator for a host adapter'
[patent_app_type] => 1
[patent_app_number] => 8/301458
[patent_app_country] => US
[patent_app_date] => 1994-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7744
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 19
[patent_words_short_claim] => 21
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/657/05657455.pdf
[firstpage_image] =>[orig_patent_app_number] => 301458
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/301458 | Status indicator for a host adapter | Sep 6, 1994 | Issued |
Array
(
[id] => 3603394
[patent_doc_number] => 05586273
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-17
[patent_title] => 'HDLC asynchronous to synchronous converter'
[patent_app_type] => 1
[patent_app_number] => 8/292563
[patent_app_country] => US
[patent_app_date] => 1994-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 5704
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/586/05586273.pdf
[firstpage_image] =>[orig_patent_app_number] => 292563
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/292563 | HDLC asynchronous to synchronous converter | Aug 17, 1994 | Issued |