Search

Alissa L Hoey

Examiner (ID: 2622, Phone: (571)272-4985 , Office: P/3765 )

Most Active Art Unit
3765
Art Unit(s)
3732, 3741, 3765
Total Applications
1780
Issued Applications
756
Pending Applications
141
Abandoned Applications
881

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16348326 [patent_doc_number] => 20200312977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => POSITIONING AIR-GAP SPACERS IN A TRANSISTOR FOR IMPROVED CONTROL OF PARASITIC CAPACITANCE [patent_app_type] => utility [patent_app_number] => 16/363355 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363355 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363355
Positioning air-gap spacers in a transistor for improved control of parasitic capacitance Mar 24, 2019 Issued
Array ( [id] => 16432857 [patent_doc_number] => 10832954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Forming a reliable wrap-around contact without source/drain sacrificial regions [patent_app_type] => utility [patent_app_number] => 16/363349 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 9588 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363349
Forming a reliable wrap-around contact without source/drain sacrificial regions Mar 24, 2019 Issued
Array ( [id] => 15000099 [patent_doc_number] => 20190319007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => LOW TEMPERATURE BONDED STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/363894 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363894 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363894
Low temperature bonded structures Mar 24, 2019 Issued
Array ( [id] => 16187180 [patent_doc_number] => 10720522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-21 [patent_title] => CMOS compatible device based on four-terminal switching lattices [patent_app_type] => utility [patent_app_number] => 16/364129 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 2691 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364129 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/364129
CMOS compatible device based on four-terminal switching lattices Mar 24, 2019 Issued
Array ( [id] => 14904309 [patent_doc_number] => 20190295920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => Multi-Package Top-Side-Cooling [patent_app_type] => utility [patent_app_number] => 16/363570 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363570 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363570
Multi-package top-side-cooling Mar 24, 2019 Issued
Array ( [id] => 17424418 [patent_doc_number] => 11257882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Active-matrix organic light-emitting diode (AMOLED) display module [patent_app_type] => utility [patent_app_number] => 16/461832 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2583 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16461832 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/461832
Active-matrix organic light-emitting diode (AMOLED) display module Mar 18, 2019 Issued
Array ( [id] => 14676943 [patent_doc_number] => 20190237586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/354394 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 45656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16354394 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/354394
Manufacturing method of semiconductor device Mar 14, 2019 Issued
Array ( [id] => 17925929 [patent_doc_number] => 11469192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Semiconductor device capable of realizing a wide band impedance matching [patent_app_type] => utility [patent_app_number] => 16/977855 [patent_app_country] => US [patent_app_date] => 2019-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 13019 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16977855 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/977855
Semiconductor device capable of realizing a wide band impedance matching Mar 5, 2019 Issued
Array ( [id] => 18205629 [patent_doc_number] => 11588037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Planar transistors with wrap-around gates and wrap-around source and drain contacts [patent_app_type] => utility [patent_app_number] => 16/289824 [patent_app_country] => US [patent_app_date] => 2019-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 21111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16289824 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/289824
Planar transistors with wrap-around gates and wrap-around source and drain contacts Feb 28, 2019 Issued
Array ( [id] => 16272287 [patent_doc_number] => 20200273775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => ACTIVE PACKAGE COOLING STRUCTURES USING MOLDED SUBSTRATE PACKAGING TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 16/287653 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/287653
Active package cooling structures using molded substrate packaging technology Feb 26, 2019 Issued
Array ( [id] => 17189092 [patent_doc_number] => 20210335977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => FAN-OUT WIRING STRUCTURE OF DISPLAY PANEL AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 16/603783 [patent_app_country] => US [patent_app_date] => 2019-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603783 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/603783
Fan-out wiring structure of display panel and display panel Feb 25, 2019 Issued
Array ( [id] => 15637549 [patent_doc_number] => 10591763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 16/285718 [patent_app_country] => US [patent_app_date] => 2019-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 46 [patent_no_of_words] => 12741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16285718 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/285718
Display device Feb 25, 2019 Issued
Array ( [id] => 15332067 [patent_doc_number] => 20200006363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => ERASABLE PROGRAMMABLE NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/281165 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5934 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281165 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281165
Erasable programmable non-volatile memory including two floating gate transistors with the same floating gate Feb 20, 2019 Issued
Array ( [id] => 16417910 [patent_doc_number] => 10825811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Gate cut first isolation formation with contact forming process mask protection [patent_app_type] => utility [patent_app_number] => 16/280343 [patent_app_country] => US [patent_app_date] => 2019-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5532 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16280343 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/280343
Gate cut first isolation formation with contact forming process mask protection Feb 19, 2019 Issued
Array ( [id] => 16433133 [patent_doc_number] => 10833233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Light-emitting device having package structure with quantum dot material and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/280465 [patent_app_country] => US [patent_app_date] => 2019-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 42 [patent_no_of_words] => 11596 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16280465 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/280465
Light-emitting device having package structure with quantum dot material and manufacturing method thereof Feb 19, 2019 Issued
Array ( [id] => 15841177 [patent_doc_number] => 20200135871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => Integrated Circuits Having Protruding Interconnect Conductors [patent_app_type] => utility [patent_app_number] => 16/280433 [patent_app_country] => US [patent_app_date] => 2019-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16280433 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/280433
Integrated circuits having protruding interconnect conductors Feb 19, 2019 Issued
Array ( [id] => 16256817 [patent_doc_number] => 20200266192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/280470 [patent_app_country] => US [patent_app_date] => 2019-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16280470 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/280470
Semiconductor structure and method for manufacturing the same Feb 19, 2019 Issued
Array ( [id] => 16324227 [patent_doc_number] => 10784199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Component inter-digitated VIAS and leads [patent_app_type] => utility [patent_app_number] => 16/280570 [patent_app_country] => US [patent_app_date] => 2019-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6097 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16280570 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/280570
Component inter-digitated VIAS and leads Feb 19, 2019 Issued
Array ( [id] => 17181467 [patent_doc_number] => 11158717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-26 [patent_title] => Method for manufacturing thin-film transistor (TFT) substrate and TFT substrate [patent_app_type] => utility [patent_app_number] => 16/485441 [patent_app_country] => US [patent_app_date] => 2019-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 8463 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16485441 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/485441
Method for manufacturing thin-film transistor (TFT) substrate and TFT substrate Feb 19, 2019 Issued
Array ( [id] => 16256815 [patent_doc_number] => 20200266190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => LOGIC CIRCUIT WITH INDIUM NITRIDE QUANTUM WELL [patent_app_type] => utility [patent_app_number] => 16/279102 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16279102 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/279102
Logic circuit with indium nitride quantum well Feb 18, 2019 Issued
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