Search

Alissa L Hoey

Examiner (ID: 2622, Phone: (571)272-4985 , Office: P/3765 )

Most Active Art Unit
3765
Art Unit(s)
3732, 3741, 3765
Total Applications
1780
Issued Applications
756
Pending Applications
141
Abandoned Applications
881

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16973817 [patent_doc_number] => 11069799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Amorphous metal hot electron transistor [patent_app_type] => utility [patent_app_number] => 16/861098 [patent_app_country] => US [patent_app_date] => 2020-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 7375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861098 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/861098
Amorphous metal hot electron transistor Apr 27, 2020 Issued
Array ( [id] => 16241564 [patent_doc_number] => 20200258798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => DEVICE AND COMPOSITION FOR FORMING ORGANIC LAYER [patent_app_type] => utility [patent_app_number] => 16/859238 [patent_app_country] => US [patent_app_date] => 2020-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16859238 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/859238
DEVICE AND COMPOSITION FOR FORMING ORGANIC LAYER Apr 26, 2020 Pending
Array ( [id] => 17189233 [patent_doc_number] => 20210336118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => BUMPLESS SUPERCONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/858812 [patent_app_country] => US [patent_app_date] => 2020-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16858812 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/858812
Forming a bumpless superconductor device by bonding two substrates via a dielectric layer Apr 26, 2020 Issued
Array ( [id] => 18016330 [patent_doc_number] => 11508637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Fan out package and methods [patent_app_type] => utility [patent_app_number] => 16/855418 [patent_app_country] => US [patent_app_date] => 2020-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 6184 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16855418 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/855418
Fan out package and methods Apr 21, 2020 Issued
Array ( [id] => 16226439 [patent_doc_number] => 20200251556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => SIDEWALL IMAGE TRANSFER NANOSHEET [patent_app_type] => utility [patent_app_number] => 16/853161 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16853161 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/853161
Sidewall image transfer nanosheet Apr 19, 2020 Issued
Array ( [id] => 18048039 [patent_doc_number] => 11521997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Multi-protrusion transfer gate structure [patent_app_type] => utility [patent_app_number] => 16/850524 [patent_app_country] => US [patent_app_date] => 2020-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 10991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16850524 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/850524
Multi-protrusion transfer gate structure Apr 15, 2020 Issued
Array ( [id] => 16364553 [patent_doc_number] => 20200321304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => DIELECTRIC AND METALLIC NANOWIRE BOND LAYERS [patent_app_type] => utility [patent_app_number] => 16/843717 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843717 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/843717
Dielectric and metallic nanowire bond layers Apr 7, 2020 Issued
Array ( [id] => 17692312 [patent_doc_number] => 20220199605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => REPAIR TECHNIQUES FOR MICRO-LED DEVICES AND ARRAYS [patent_app_type] => utility [patent_app_number] => 17/601968 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17601968 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/601968
REPAIR TECHNIQUES FOR MICRO-LED DEVICES AND ARRAYS Apr 7, 2020 Pending
Array ( [id] => 17145406 [patent_doc_number] => 20210313419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 16/842066 [patent_app_country] => US [patent_app_date] => 2020-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16842066 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/842066
Semiconductor device including gate barrier layer Apr 6, 2020 Issued
Array ( [id] => 16332477 [patent_doc_number] => 20200303443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => FABRICATION OF OPTICAL METASURFACES [patent_app_type] => utility [patent_app_number] => 16/841413 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16841413 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/841413
Fabrication of optical metasurfaces Apr 5, 2020 Issued
Array ( [id] => 17152528 [patent_doc_number] => 11145619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Electrical connecting structure having nano-twins copper and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/836955 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5189 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836955 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836955
Electrical connecting structure having nano-twins copper and method of forming the same Mar 31, 2020 Issued
Array ( [id] => 16180296 [patent_doc_number] => 20200227265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SILICIDE FILMS THROUGH SELECTIVE DEPOSITION [patent_app_type] => utility [patent_app_number] => 16/836858 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836858 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836858
Silicide films through selective deposition Mar 30, 2020 Issued
Array ( [id] => 16479821 [patent_doc_number] => 10854778 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-01 [patent_title] => Manufacturable display based on thin film gallium and nitrogen containing light emitting diodes [patent_app_type] => utility [patent_app_number] => 16/835082 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 68 [patent_no_of_words] => 47489 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16835082 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/835082
Manufacturable display based on thin film gallium and nitrogen containing light emitting diodes Mar 29, 2020 Issued
Array ( [id] => 16180578 [patent_doc_number] => 20200227547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SEMICONDUCTOR DEVICES WITH DOPED REGIONS FUNCTIONING AS ENHANCED RESISTIVITY REGIONS OR DIFFUSION BARRIERS, AND METHODS OF FABRICATION THEREFOR [patent_app_type] => utility [patent_app_number] => 16/834322 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834322 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834322
Semiconductor devices with doped regions functioning as enhanced resistivity regions or diffusion barriers, and methods of fabrication therefor Mar 29, 2020 Issued
Array ( [id] => 16226222 [patent_doc_number] => 20200251339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => METHODS OF FORMING STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/834766 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834766 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834766
Methods of forming structures utilizing self-assembling nucleic acids Mar 29, 2020 Issued
Array ( [id] => 17025709 [patent_doc_number] => 20210249581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => HEAT FLOW SWITCHING ELEMENT [patent_app_type] => utility [patent_app_number] => 16/830847 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16830847 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/830847
Heat flow switching element Mar 25, 2020 Issued
Array ( [id] => 17630548 [patent_doc_number] => 20220165563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => METHOD FOR PROVIDING DOPED SILICON [patent_app_type] => utility [patent_app_number] => 17/441178 [patent_app_country] => US [patent_app_date] => 2020-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17441178 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/441178
METHOD FOR PROVIDING DOPED SILICON Mar 16, 2020 Pending
Array ( [id] => 16479677 [patent_doc_number] => 10854633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Semiconductor memory device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/815096 [patent_app_country] => US [patent_app_date] => 2020-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 6466 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16815096 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/815096
Semiconductor memory device and method of manufacturing the same Mar 10, 2020 Issued
Array ( [id] => 16119763 [patent_doc_number] => 20200211904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SEMICONDUCTOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/811257 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16811257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/811257
Semiconductor structures Mar 5, 2020 Issued
Array ( [id] => 16987896 [patent_doc_number] => 11075078 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-27 [patent_title] => Method for making a semiconductor device including a superlattice within a recessed etch [patent_app_type] => utility [patent_app_number] => 16/810957 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 5494 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16810957 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/810957
Method for making a semiconductor device including a superlattice within a recessed etch Mar 5, 2020 Issued
Menu