
Allan R. Wilson
Examiner (ID: 12196, Phone: (571)272-1738 , Office: P/2897 )
| Most Active Art Unit | 2897 |
| Art Unit(s) | 2897, 2503, 3621, 2815 |
| Total Applications | 1911 |
| Issued Applications | 1758 |
| Pending Applications | 18 |
| Abandoned Applications | 144 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 770170
[patent_doc_number] => 07005703
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-28
[patent_title] => 'Metal-oxide-semiconductor device having improved performance and reliability'
[patent_app_type] => utility
[patent_app_number] => 10/688231
[patent_app_country] => US
[patent_app_date] => 2003-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 5677
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[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/005/07005703.pdf
[firstpage_image] =>[orig_patent_app_number] => 10688231
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/688231 | Metal-oxide-semiconductor device having improved performance and reliability | Oct 16, 2003 | Issued |
Array
(
[id] => 738863
[patent_doc_number] => 07034362
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-25
[patent_title] => 'Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures'
[patent_app_type] => utility
[patent_app_number] => 10/688692
[patent_app_country] => US
[patent_app_date] => 2003-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => patents/07/034/07034362.pdf
[firstpage_image] =>[orig_patent_app_number] => 10688692
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/688692 | Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures | Oct 16, 2003 | Issued |
Array
(
[id] => 7291651
[patent_doc_number] => 20040211958
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Semiconductor device having a conductive layer and a manufacturing method thereof'
[patent_app_type] => new
[patent_app_number] => 10/682902
[patent_app_country] => US
[patent_app_date] => 2003-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => publications/A1/0211/20040211958.pdf
[firstpage_image] =>[orig_patent_app_number] => 10682902
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/682902 | Semiconductor device having a conductive layer and a manufacturing method thereof | Oct 13, 2003 | Abandoned |
Array
(
[id] => 949072
[patent_doc_number] => 06963108
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-11-08
[patent_title] => 'Recessed channel'
[patent_app_type] => utility
[patent_app_number] => 10/683631
[patent_app_country] => US
[patent_app_date] => 2003-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/06/963/06963108.pdf
[firstpage_image] =>[orig_patent_app_number] => 10683631
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/683631 | Recessed channel | Oct 9, 2003 | Issued |
Array
(
[id] => 708632
[patent_doc_number] => 07061047
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-13
[patent_title] => 'Semiconductor device having trench gate structure and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/682111
[patent_app_country] => US
[patent_app_date] => 2003-10-10
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[pdf_file] => patents/07/061/07061047.pdf
[firstpage_image] =>[orig_patent_app_number] => 10682111
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/682111 | Semiconductor device having trench gate structure and manufacturing method thereof | Oct 9, 2003 | Issued |
Array
(
[id] => 672941
[patent_doc_number] => 07091540
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-15
[patent_title] => 'Recess transistor (TR) gate to obtain large self-aligned contact (SAC) open margin'
[patent_app_type] => utility
[patent_app_number] => 10/682492
[patent_app_country] => US
[patent_app_date] => 2003-10-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/091/07091540.pdf
[firstpage_image] =>[orig_patent_app_number] => 10682492
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/682492 | Recess transistor (TR) gate to obtain large self-aligned contact (SAC) open margin | Oct 9, 2003 | Issued |
Array
(
[id] => 7147731
[patent_doc_number] => 20050023589
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'Semiconductor memory device having a ferroelectric capacitor and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/679152
[patent_app_country] => US
[patent_app_date] => 2003-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 41
[patent_no_of_words] => 11554
[patent_no_of_claims] => 20
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[pdf_file] => publications/A1/0023/20050023589.pdf
[firstpage_image] =>[orig_patent_app_number] => 10679152
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/679152 | Semiconductor memory device having a ferroelectric capacitor | Oct 5, 2003 | Issued |
Array
(
[id] => 7161789
[patent_doc_number] => 20050084984
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Method for forming ferrocapacitors and FeRAM devices'
[patent_app_type] => utility
[patent_app_number] => 10/678952
[patent_app_country] => US
[patent_app_date] => 2003-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 2180
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[pdf_file] => publications/A1/0084/20050084984.pdf
[firstpage_image] =>[orig_patent_app_number] => 10678952
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/678952 | Method for forming ferrocapacitors and FeRAM devices | Oct 1, 2003 | Abandoned |
Array
(
[id] => 996525
[patent_doc_number] => 06913964
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-05
[patent_title] => 'Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region'
[patent_app_type] => utility
[patent_app_number] => 10/676695
[patent_app_country] => US
[patent_app_date] => 2003-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/06/913/06913964.pdf
[firstpage_image] =>[orig_patent_app_number] => 10676695
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/676695 | Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region | Sep 29, 2003 | Issued |
Array
(
[id] => 734166
[patent_doc_number] => 07038288
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-02
[patent_title] => 'Front side illuminated photodiode with backside bump'
[patent_app_type] => utility
[patent_app_number] => 10/669081
[patent_app_country] => US
[patent_app_date] => 2003-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 4997
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[pdf_file] => patents/07/038/07038288.pdf
[firstpage_image] =>[orig_patent_app_number] => 10669081
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/669081 | Front side illuminated photodiode with backside bump | Sep 22, 2003 | Issued |
Array
(
[id] => 793444
[patent_doc_number] => 06982490
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-01-03
[patent_title] => 'Interface device including a video BIOS component'
[patent_app_type] => utility
[patent_app_number] => 10/666085
[patent_app_country] => US
[patent_app_date] => 2003-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4057
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[pdf_file] => patents/06/982/06982490.pdf
[firstpage_image] =>[orig_patent_app_number] => 10666085
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/666085 | Interface device including a video BIOS component | Sep 18, 2003 | Issued |
Array
(
[id] => 6975378
[patent_doc_number] => 20050285093
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'Magnetic storage device using ferromagnetic tunnel junction element'
[patent_app_type] => utility
[patent_app_number] => 10/530271
[patent_app_country] => US
[patent_app_date] => 2003-09-18
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[firstpage_image] =>[orig_patent_app_number] => 10530271
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/530271 | Magnetic storage device using ferromagnetic tunnel junction element | Sep 17, 2003 | Issued |
Array
(
[id] => 721232
[patent_doc_number] => 07049659
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-23
[patent_title] => 'Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation'
[patent_app_type] => utility
[patent_app_number] => 10/658772
[patent_app_country] => US
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[pdf_file] => patents/07/049/07049659.pdf
[firstpage_image] =>[orig_patent_app_number] => 10658772
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/658772 | Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation | Sep 9, 2003 | Issued |
Array
(
[id] => 944325
[patent_doc_number] => 06967379
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-22
[patent_title] => 'Semiconductor device including metal insulator semiconductor field effect transistor'
[patent_app_type] => utility
[patent_app_number] => 10/658371
[patent_app_country] => US
[patent_app_date] => 2003-09-10
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[pdf_file] => patents/06/967/06967379.pdf
[firstpage_image] =>[orig_patent_app_number] => 10658371
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/658371 | Semiconductor device including metal insulator semiconductor field effect transistor | Sep 9, 2003 | Issued |
Array
(
[id] => 1074046
[patent_doc_number] => 06838711
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-01-04
[patent_title] => 'Power MOS arrays with non-uniform polygate length'
[patent_app_type] => utility
[patent_app_number] => 10/658432
[patent_app_country] => US
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[pdf_file] => patents/06/838/06838711.pdf
[firstpage_image] =>[orig_patent_app_number] => 10658432
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/658432 | Power MOS arrays with non-uniform polygate length | Sep 7, 2003 | Issued |
Array
(
[id] => 7144018
[patent_doc_number] => 20040169255
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-02
[patent_title] => 'Semiconductor device and method of manufacturing same'
[patent_app_type] => new
[patent_app_number] => 10/654472
[patent_app_country] => US
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[pdf_file] => publications/A1/0169/20040169255.pdf
[firstpage_image] =>[orig_patent_app_number] => 10654472
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/654472 | Semiconductor device and capacitor | Sep 3, 2003 | Issued |
Array
(
[id] => 7198313
[patent_doc_number] => 20050051808
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-10
[patent_title] => 'DUAL GATE BCMD PIXEL SUITABLE FOR HIGH PERFORMANCE CMOS IMAGE SENSOR ARRAYS'
[patent_app_type] => utility
[patent_app_number] => 10/654451
[patent_app_country] => US
[patent_app_date] => 2003-09-04
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[firstpage_image] =>[orig_patent_app_number] => 10654451
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/654451 | Dual gate BCMD pixel suitable for high performance CMOS image sensor arrays | Sep 3, 2003 | Issued |
Array
(
[id] => 703114
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[patent_title] => 'Supression of dark current in a photosensor for imaging'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/653152 | Supression of dark current in a photosensor for imaging | Sep 2, 2003 | Issued |
Array
(
[id] => 7080538
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[patent_title] => 'Hybrid vertical twisted bitline architecture'
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[firstpage_image] =>[orig_patent_app_number] => 10653741
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/653741 | Hybrid vertical twisted bitline architecture | Sep 1, 2003 | Abandoned |
Array
(
[id] => 7154372
[patent_doc_number] => 20050082596
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => '[FLASH MEMORY AND METHOD FOR MANUFACTURING THE SAME]'
[patent_app_type] => utility
[patent_app_number] => 10/604882
[patent_app_country] => US
[patent_app_date] => 2003-08-25
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[pdf_file] => publications/A1/0082/20050082596.pdf
[firstpage_image] =>[orig_patent_app_number] => 10604882
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604882 | Flash memory | Aug 24, 2003 | Issued |