Search

Allan R. Wilson

Examiner (ID: 12196, Phone: (571)272-1738 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2503, 3621, 2815
Total Applications
1911
Issued Applications
1758
Pending Applications
18
Abandoned Applications
144

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1132422 [patent_doc_number] => 06787861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Non-crystalline oxides for use in microelectronic, optical, and other applications' [patent_app_type] => B2 [patent_app_number] => 09/891552 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4565 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787861.pdf [firstpage_image] =>[orig_patent_app_number] => 09891552 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/891552
Non-crystalline oxides for use in microelectronic, optical, and other applications Jun 24, 2001 Issued
Array ( [id] => 6985503 [patent_doc_number] => 20010035524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Josephson junction array device, and manufacture thereof' [patent_app_type] => new [patent_app_number] => 09/885833 [patent_app_country] => US [patent_app_date] => 2001-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11990 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20010035524.pdf [firstpage_image] =>[orig_patent_app_number] => 09885833 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/885833
Josephson junction array device, and manufacture thereof Jun 19, 2001 Abandoned
Array ( [id] => 217518 [patent_doc_number] => 07612430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Silicon bipolar transistor, circuit arrangement and method for producing a silicon bipolar transistor' [patent_app_type] => utility [patent_app_number] => 10/297421 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3737 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/612/07612430.pdf [firstpage_image] =>[orig_patent_app_number] => 10297421 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/297421
Silicon bipolar transistor, circuit arrangement and method for producing a silicon bipolar transistor Jun 14, 2001 Issued
90/006029 ESD PROTECTION IMPROVEMENT Jun 6, 2001 Issued
Array ( [id] => 6221347 [patent_doc_number] => 20020003048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Metal interconnections and active matrix substrate using the same' [patent_app_type] => new [patent_app_number] => 09/866121 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7170 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003048.pdf [firstpage_image] =>[orig_patent_app_number] => 09866121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866121
Metal interconnections and active matrix substrate using the same May 24, 2001 Issued
Array ( [id] => 6888534 [patent_doc_number] => 20010023989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Semiconductor dielectric structure and method for making the same' [patent_app_type] => new [patent_app_number] => 09/864441 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4804 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20010023989.pdf [firstpage_image] =>[orig_patent_app_number] => 09864441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864441
Semiconductor dielectric structure and method for making the same May 22, 2001 Abandoned
Array ( [id] => 6285100 [patent_doc_number] => 20020053738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'SEMICONDUCTOR DEVICE WITH IMPROVED METAL INTERCONNECTION AND METHOD FOR FORMING THE METAL INTERCONNECTION' [patent_app_type] => new [patent_app_number] => 09/862521 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4852 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053738.pdf [firstpage_image] =>[orig_patent_app_number] => 09862521 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/862521
Semiconductor device with improved metal interconnection and method for forming the metal interconnection May 22, 2001 Issued
Array ( [id] => 6897491 [patent_doc_number] => 20010045656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Multilayer wiring structure for semiconductor device' [patent_app_type] => new [patent_app_number] => 09/863451 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1815 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20010045656.pdf [firstpage_image] =>[orig_patent_app_number] => 09863451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/863451
Multilayer wiring structure for semiconductor device May 21, 2001 Abandoned
Array ( [id] => 1347412 [patent_doc_number] => 06586830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-01 [patent_title] => 'Semiconductor device with an interposer' [patent_app_type] => B2 [patent_app_number] => 09/860042 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 5575 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/586/06586830.pdf [firstpage_image] =>[orig_patent_app_number] => 09860042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/860042
Semiconductor device with an interposer May 16, 2001 Issued
Array ( [id] => 1420620 [patent_doc_number] => 06512280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-28 [patent_title] => 'Integrated CMOS structure for gate-controlled buried photodiode' [patent_app_type] => B2 [patent_app_number] => 09/859121 [patent_app_country] => US [patent_app_date] => 2001-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3837 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/512/06512280.pdf [firstpage_image] =>[orig_patent_app_number] => 09859121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/859121
Integrated CMOS structure for gate-controlled buried photodiode May 15, 2001 Issued
Array ( [id] => 5840445 [patent_doc_number] => 20020130422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Semiconductor/printed circuit board assembly, and computer system' [patent_app_type] => new [patent_app_number] => 09/855731 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3644 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20020130422.pdf [firstpage_image] =>[orig_patent_app_number] => 09855731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/855731
Semiconductor/printed circuit board assembly May 14, 2001 Issued
Array ( [id] => 6107213 [patent_doc_number] => 20020171147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Structure of a dual damascene via' [patent_app_type] => new [patent_app_number] => 09/854961 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5251 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20020171147.pdf [firstpage_image] =>[orig_patent_app_number] => 09854961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/854961
Structure of a dual damascene via May 14, 2001 Abandoned
Array ( [id] => 1452369 [patent_doc_number] => 06455936 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Integrated circuit assembly having interposer with a compliant layer' [patent_app_type] => B1 [patent_app_number] => 09/855231 [patent_app_country] => US [patent_app_date] => 2001-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455936.pdf [firstpage_image] =>[orig_patent_app_number] => 09855231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/855231
Integrated circuit assembly having interposer with a compliant layer May 13, 2001 Issued
Array ( [id] => 1536539 [patent_doc_number] => 06489676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-03 [patent_title] => 'Semiconductor device having an interconnecting post formed on an interposer within a sealing resin' [patent_app_type] => B2 [patent_app_number] => 09/843912 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4981 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489676.pdf [firstpage_image] =>[orig_patent_app_number] => 09843912 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/843912
Semiconductor device having an interconnecting post formed on an interposer within a sealing resin Apr 29, 2001 Issued
Array ( [id] => 1452394 [patent_doc_number] => 06455943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Bonding pad structure of semiconductor device having improved bondability' [patent_app_type] => B1 [patent_app_number] => 09/840720 [patent_app_country] => US [patent_app_date] => 2001-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3040 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455943.pdf [firstpage_image] =>[orig_patent_app_number] => 09840720 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/840720
Bonding pad structure of semiconductor device having improved bondability Apr 23, 2001 Issued
Array ( [id] => 6947943 [patent_doc_number] => 20010021578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Interconnect structure of semiconductor device and method for manufacturing same' [patent_app_type] => new [patent_app_number] => 09/836171 [patent_app_country] => US [patent_app_date] => 2001-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3341 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021578.pdf [firstpage_image] =>[orig_patent_app_number] => 09836171 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/836171
Interconnect structure of semiconductor device and method for manufacturing same Apr 17, 2001 Abandoned
Array ( [id] => 1476386 [patent_doc_number] => 06388316 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Semiconductor module' [patent_app_type] => B1 [patent_app_number] => 09/835582 [patent_app_country] => US [patent_app_date] => 2001-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3887 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388316.pdf [firstpage_image] =>[orig_patent_app_number] => 09835582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/835582
Semiconductor module Apr 16, 2001 Issued
Array ( [id] => 6921615 [patent_doc_number] => 20010029100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Microelectronic Contacts' [patent_app_type] => new [patent_app_number] => 09/834192 [patent_app_country] => US [patent_app_date] => 2001-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5965 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20010029100.pdf [firstpage_image] =>[orig_patent_app_number] => 09834192 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/834192
Microelectronic contacts Apr 11, 2001 Issued
Array ( [id] => 1509498 [patent_doc_number] => 06441483 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Die stacking scheme' [patent_app_type] => B1 [patent_app_number] => 09/804421 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5557 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441483.pdf [firstpage_image] =>[orig_patent_app_number] => 09804421 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/804421
Die stacking scheme Mar 29, 2001 Issued
Array ( [id] => 6843211 [patent_doc_number] => 20030148558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Integrated circuit and method of manufacturing thereof' [patent_app_type] => new [patent_app_number] => 10/240651 [patent_app_country] => US [patent_app_date] => 2002-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 13939 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20030148558.pdf [firstpage_image] =>[orig_patent_app_number] => 10240651 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/240651
Integrated circuit device having reduced substrate size and a method for manufacturing the same Mar 29, 2001 Issued
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