Allan R. Wilson

Array ( [id] => 6986888 [patent_doc_number] => 20010036720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Semiconductor component and method for manufacturing it' [patent_app_type] => new [patent_app_number] => 09/816931 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3206 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20010036720.pdf [firstpage_image] =>[orig_patent_app_number] => 09816931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1218012 [patent_doc_number] => 06707121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Micro electro mechanical systems and devices' [patent_app_type] => B2 [patent_app_number] => 09/816611 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 20 [patent_no_of_words] => 9798 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707121.pdf [firstpage_image] =>[orig_patent_app_number] => 09816611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1422615 [patent_doc_number] => 06518652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-11 [patent_title] => 'Semiconductor package' [patent_app_type] => B2 [patent_app_number] => 09/808151 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 7636 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518652.pdf [firstpage_image] =>[orig_patent_app_number] => 09808151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 991081 [patent_doc_number] => 06919608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Spin transistor' [patent_app_type] => utility [patent_app_number] => 10/221566 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5944 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/919/06919608.pdf [firstpage_image] =>[orig_patent_app_number] => 10221566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6959544 [patent_doc_number] => 20010011737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'Photodetector and device employing the photodetector for converting an optical signal into an electrical signal' [patent_app_type] => new [patent_app_number] => 09/798002 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7491 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20010011737.pdf [firstpage_image] =>[orig_patent_app_number] => 09798002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6896050 [patent_doc_number] => 20010026840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Method of metalizing a semiconductor power device ceramic member' [patent_app_type] => new [patent_app_number] => 09/792672 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2569 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026840.pdf [firstpage_image] =>[orig_patent_app_number] => 09792672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1563130 [patent_doc_number] => 06362520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Microelectronic mounting with multiple lead deformation using restraining straps' [patent_app_type] => B1 [patent_app_number] => 09/791245 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 6039 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362520.pdf [firstpage_image] =>[orig_patent_app_number] => 09791245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1502331 [patent_doc_number] => 06486534 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Integrated circuit die having an interference shield' [patent_app_type] => B1 [patent_app_number] => 09/785620 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486534.pdf [firstpage_image] =>[orig_patent_app_number] => 09785620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6547310 [patent_doc_number] => 20020110949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Charge-coupled device wafer cover plate with compact interconnect wiring' [patent_app_type] => new [patent_app_number] => 09/781122 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 5361 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20020110949.pdf [firstpage_image] =>[orig_patent_app_number] => 09781122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1576418 [patent_doc_number] => 06469384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Unmolded package for a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/776341 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1456 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469384.pdf [firstpage_image] =>[orig_patent_app_number] => 09776341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6000007 [patent_doc_number] => 20020028550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Semiconductor integrated circuit device and method of manufacturing the same, and cell size calculation method for DRAM memory cells' [patent_app_type] => new [patent_app_number] => 09/760804 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9076 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20020028550.pdf [firstpage_image] =>[orig_patent_app_number] => 09760804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6946946 [patent_doc_number] => 20010020707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 09/759300 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9038 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20010020707.pdf [firstpage_image] =>[orig_patent_app_number] => 09759300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6300473 [patent_doc_number] => 20020093054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Front stage process of a fully depleted silicon-on-insulator device and a structure thereof' [patent_app_type] => new [patent_app_number] => 09/759971 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3657 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20020093054.pdf [firstpage_image] =>[orig_patent_app_number] => 09759971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1491809 [patent_doc_number] => 06417541 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'ESD protection network with field oxide device and bonding pad' [patent_app_type] => B1 [patent_app_number] => 09/759492 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3644 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417541.pdf [firstpage_image] =>[orig_patent_app_number] => 09759492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1529574 [patent_doc_number] => 06479898 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Dielectric treatment in integrated circuit interconnects' [patent_app_type] => B1 [patent_app_number] => 09/760421 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3340 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479898.pdf [firstpage_image] =>[orig_patent_app_number] => 09760421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7645215 [patent_doc_number] => 06472757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-29 [patent_title] => 'Conductor reservoir volume for integrated circuit interconnects' [patent_app_type] => B2 [patent_app_number] => 09/758994 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3522 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472757.pdf [firstpage_image] =>[orig_patent_app_number] => 09758994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1387189 [patent_doc_number] => 06555909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Seedless barrier layers in integrated circuits and a method of manufacture therefor' [patent_app_type] => B1 [patent_app_number] => 09/760422 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3501 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555909.pdf [firstpage_image] =>[orig_patent_app_number] => 09760422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1420862 [patent_doc_number] => 06512300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-28 [patent_title] => 'Water level interconnection' [patent_app_type] => B2 [patent_app_number] => 09/756801 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1467 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/512/06512300.pdf [firstpage_image] =>[orig_patent_app_number] => 09756801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6893125 [patent_doc_number] => 20010015491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Printed-wiring substrate having lead pins' [patent_app_type] => new [patent_app_number] => 09/756751 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6056 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015491.pdf [firstpage_image] =>[orig_patent_app_number] => 09756751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6572284 [patent_doc_number] => 20020014648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/756222 [patent_app_country] => US [patent_app_date] => 2001-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 15798 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20020014648.pdf [firstpage_image] =>[orig_patent_app_number] => 09756222 [rel_patent_id] =>[rel_patent_doc_number] =>)