Search

Allen Chan

Examiner (ID: 10119, Phone: (571)270-5529 , Office: P/3714 )

Most Active Art Unit
3715
Art Unit(s)
3718, 3714, 3715
Total Applications
946
Issued Applications
686
Pending Applications
53
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16794769 [patent_doc_number] => 20210124586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => APPARATUS AND METHOD FOR HANDLING INCORRECT BRANCH DIRECTION PREDICTIONS [patent_app_type] => utility [patent_app_number] => 16/662438 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662438 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/662438
Apparatus and method for handling incorrect branch direction predictions Oct 23, 2019 Issued
Array ( [id] => 17492163 [patent_doc_number] => 11281466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Register renaming after a non-pickable scheduler queue [patent_app_type] => utility [patent_app_number] => 16/660495 [patent_app_country] => US [patent_app_date] => 2019-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4239 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660495 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/660495
Register renaming after a non-pickable scheduler queue Oct 21, 2019 Issued
Array ( [id] => 18547430 [patent_doc_number] => 11720783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Multiplication and addition device for matrices, neural network computing device, and method [patent_app_type] => utility [patent_app_number] => 16/658800 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4278 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658800 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/658800
Multiplication and addition device for matrices, neural network computing device, and method Oct 20, 2019 Issued
Array ( [id] => 15500597 [patent_doc_number] => 20200050487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => System and Method for Low Latency Node Local Scheduling in Distributed Resource Management [patent_app_type] => utility [patent_app_number] => 16/658699 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658699 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/658699
System and method for low latency node local scheduling in distributed resource management Oct 20, 2019 Issued
Array ( [id] => 17492164 [patent_doc_number] => 11281467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Maintaining prediction data used to predict whether a branch represented by a branch instruction will be taken [patent_app_type] => utility [patent_app_number] => 16/654372 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4907 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654372 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654372
Maintaining prediction data used to predict whether a branch represented by a branch instruction will be taken Oct 15, 2019 Issued
Array ( [id] => 18104181 [patent_doc_number] => 11544067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Accelerating AI training by an all-reduce process with compression over a distributed system [patent_app_type] => utility [patent_app_number] => 16/607087 [patent_app_country] => US [patent_app_date] => 2019-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5339 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16607087 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/607087
Accelerating AI training by an all-reduce process with compression over a distributed system Oct 11, 2019 Issued
Array ( [id] => 15685261 [patent_doc_number] => 20200097294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => METHOD FOR MANAGING THE SUPPLY OF INFORMATION, SUCH AS INSTRUCTIONS, TO A MICROPROCESSOR, AND A CORRESPONDING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/573299 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573299 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/573299
Method for managing the supply of information, such as instructions, to a microprocessor, and a corresponding system Sep 16, 2019 Issued
Array ( [id] => 17276524 [patent_doc_number] => 20210382722 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2021-12-09 [patent_title] => Reconfigurable Parallel Processing [patent_app_type] => utility [patent_app_number] => 16/569749 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569749 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/569749
Reconfigurable parallel processing Sep 12, 2019 Issued
Array ( [id] => 17276524 [patent_doc_number] => 20210382722 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2021-12-09 [patent_title] => Reconfigurable Parallel Processing [patent_app_type] => utility [patent_app_number] => 16/569749 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569749 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/569749
Reconfigurable parallel processing Sep 12, 2019 Issued
Array ( [id] => 16486157 [patent_doc_number] => 20200379762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => LOOK-UP TABLE READ [patent_app_type] => utility [patent_app_number] => 16/570640 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/570640
Look-up table read Sep 12, 2019 Issued
Array ( [id] => 16690522 [patent_doc_number] => 20210073000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => REUSING ADJACENT SIMD UNIT FOR FAST WIDE RESULT GENERATION [patent_app_type] => utility [patent_app_number] => 16/565946 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16565946 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/565946
Reusing adjacent SIMD unit for fast wide result generation Sep 9, 2019 Issued
Array ( [id] => 15328429 [patent_doc_number] => 20200004544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => DETERMINING AND PREDICTING DERIVED VALUES [patent_app_type] => utility [patent_app_number] => 16/562959 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562959 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/562959
Determining and predicting derived values Sep 5, 2019 Issued
Array ( [id] => 15328419 [patent_doc_number] => 20200004539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => CODE-SPECIFIC AFFILIATED REGISTER PREDICTION [patent_app_type] => utility [patent_app_number] => 16/562906 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562906 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/562906
Code-specific affiliated register prediction Sep 5, 2019 Issued
Array ( [id] => 16584777 [patent_doc_number] => 20210019179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => K-TIER ARCHITECTURE SCHEDULING [patent_app_type] => utility [patent_app_number] => 16/516513 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516513 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516513
K-tier architecture scheduling Jul 18, 2019 Issued
Array ( [id] => 17143729 [patent_doc_number] => 20210311742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => AN APPARATUS AND METHOD FOR PREDICTING SOURCE OPERAND VALUES AND OPTIMIZED PROCESSING OF INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/266759 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17266759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/266759
Apparatus and method for predicting source operand values and optimized processing of instructions Jul 16, 2019 Issued
Array ( [id] => 16818628 [patent_doc_number] => 11003454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Apparatus and method for speculative execution of instructions [patent_app_type] => utility [patent_app_number] => 16/514124 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8092 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514124 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/514124
Apparatus and method for speculative execution of instructions Jul 16, 2019 Issued
Array ( [id] => 15090339 [patent_doc_number] => 20190339980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => MEMORY-BASED DISTRIBUTED PROCESSOR ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/512562 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512562 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/512562
Memory-based distributed processor architecture Jul 15, 2019 Issued
Array ( [id] => 17106294 [patent_doc_number] => 11126511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Memory-based distributed processor architecture [patent_app_type] => utility [patent_app_number] => 16/512622 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 36285 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512622 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/512622
Memory-based distributed processor architecture Jul 15, 2019 Issued
Array ( [id] => 16879803 [patent_doc_number] => 11029950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Reducing latency of common source data movement instructions [patent_app_type] => utility [patent_app_number] => 16/502231 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502231 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502231
Reducing latency of common source data movement instructions Jul 2, 2019 Issued
Array ( [id] => 15500535 [patent_doc_number] => 20200050456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => Method for Processing Information, and Processor [patent_app_type] => utility [patent_app_number] => 16/502628 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502628 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502628
Processor, and method for processing information applied to processor Jul 2, 2019 Issued
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