Search

Allen Chan

Examiner (ID: 10119, Phone: (571)270-5529 , Office: P/3714 )

Most Active Art Unit
3715
Art Unit(s)
3718, 3714, 3715
Total Applications
946
Issued Applications
686
Pending Applications
53
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16543298 [patent_doc_number] => 20200409713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => CORE-TO-CORE END "OFFLOAD" INSTRUCTION(S) [patent_app_type] => utility [patent_app_number] => 16/457970 [patent_app_country] => US [patent_app_date] => 2019-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457970 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/457970
Core-to-core end "offload" instruction(s) Jun 28, 2019 Issued
Array ( [id] => 17771156 [patent_doc_number] => 11403097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Systems and methods to skip inconsequential matrix operations [patent_app_type] => utility [patent_app_number] => 16/453724 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 51 [patent_no_of_words] => 27245 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453724 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453724
Systems and methods to skip inconsequential matrix operations Jun 25, 2019 Issued
Array ( [id] => 16200616 [patent_doc_number] => 10725779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Method and apparatus to process SHA-2 secure hashing algorithm [patent_app_type] => utility [patent_app_number] => 16/450319 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 19536 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450319 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/450319
Method and apparatus to process SHA-2 secure hashing algorithm Jun 23, 2019 Issued
Array ( [id] => 15328431 [patent_doc_number] => 20200004545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => INFORMATION PROCESSING DEVICE AND NON-TRANSITORY COMPUTER READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 16/442567 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16442567 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/442567
INFORMATION PROCESSING DEVICE AND NON-TRANSITORY COMPUTER READABLE MEDIUM Jun 16, 2019 Abandoned
Array ( [id] => 16454630 [patent_doc_number] => 20200364056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => FACILITATING DATA PROCESSING USING SIMD REDUCTION OPERATIONS ACROSS SIMD LANES [patent_app_type] => utility [patent_app_number] => 16/412072 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412072 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412072
Facilitating data processing using SIMD reduction operations across SIMD lanes May 13, 2019 Issued
Array ( [id] => 16431416 [patent_doc_number] => 10831498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Managing an issue queue for fused instructions and paired instructions in a microprocessor [patent_app_type] => utility [patent_app_number] => 16/409993 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7265 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16409993 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/409993
Managing an issue queue for fused instructions and paired instructions in a microprocessor May 12, 2019 Issued
Array ( [id] => 17252843 [patent_doc_number] => 11188332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => System and handling of register data in processors [patent_app_type] => utility [patent_app_number] => 16/408687 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10471 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408687 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/408687
System and handling of register data in processors May 9, 2019 Issued
Array ( [id] => 16706226 [patent_doc_number] => 10956158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => System and handling of register data in processors [patent_app_type] => utility [patent_app_number] => 16/408749 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 11187 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408749 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/408749
System and handling of register data in processors May 9, 2019 Issued
Array ( [id] => 17202057 [patent_doc_number] => 20210342152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => HANDLING LOAD-EXCLUSIVE INSTRUCTIONS IN APPARATUS HAVING SUPPORT FOR TRANSACTIONAL MEMORY [patent_app_type] => utility [patent_app_number] => 17/255001 [patent_app_country] => US [patent_app_date] => 2019-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17255001 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/255001
Handling load-exclusive instructions in apparatus having support for transactional memory May 8, 2019 Issued
Array ( [id] => 15090425 [patent_doc_number] => 20190340023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Memory Request Size Management in a Multi-Threaded, Self-Scheduling Processor [patent_app_type] => utility [patent_app_number] => 16/399800 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399800 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399800
Memory request size management in a multi-threaded, self-scheduling processor Apr 29, 2019 Issued
Array ( [id] => 15090687 [patent_doc_number] => 20190340154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Multi-Threaded, Self-Scheduling Processor [patent_app_type] => utility [patent_app_number] => 16/399588 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399588
Multi-threaded, self-scheduling processor Apr 29, 2019 Issued
Array ( [id] => 15090423 [patent_doc_number] => 20190340022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Thread State Monitoring in a System Having a Multi-Threaded, Self-Scheduling Processor [patent_app_type] => utility [patent_app_number] => 16/399769 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399769 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399769
Thread state monitoring in a system having a multi-threaded, self-scheduling processor Apr 29, 2019 Issued
Array ( [id] => 15090427 [patent_doc_number] => 20190340024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Thread Creation on Local or Remote Compute Elements by a Multi-Threaded, Self-Scheduling Processor [patent_app_type] => utility [patent_app_number] => 16/399817 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399817 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399817
Thread creation on local or remote compute elements by a multi-threaded, self-scheduling processor Apr 29, 2019 Issued
Array ( [id] => 15090331 [patent_doc_number] => 20190339976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Thread Commencement Using a Work Descriptor Packet in a Self-Scheduling Processor [patent_app_type] => utility [patent_app_number] => 16/399615 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399615 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399615
Thread commencement using a work descriptor packet in a self-scheduling processor Apr 29, 2019 Issued
Array ( [id] => 15090417 [patent_doc_number] => 20190340019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Thread Commencement and Completion Using Work Descriptor Packets in a System Having a Self-Scheduling Processor and a Hybrid Threading Fabric [patent_app_type] => utility [patent_app_number] => 16/399642 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399642 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399642
Thread commencement and completion using work descriptor packets in a system having a self-scheduling processor and a hybrid threading fabric Apr 29, 2019 Issued
Array ( [id] => 15090689 [patent_doc_number] => 20190340155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Event Messaging in a System Having a Self-Scheduling Processor and a Hybrid Threading Fabric [patent_app_type] => utility [patent_app_number] => 16/399672 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399672 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399672
Event messaging in a system having a self-scheduling processor and a hybrid threading fabric Apr 29, 2019 Issued
Array ( [id] => 16844680 [patent_doc_number] => 11016765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Bit string operations using a computing tile [patent_app_type] => utility [patent_app_number] => 16/397148 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 18919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/397148
Bit string operations using a computing tile Apr 28, 2019 Issued
Array ( [id] => 16400903 [patent_doc_number] => 20200341761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => BIT STING OPERATIONS USING A COMPUTING TILE [patent_app_type] => utility [patent_app_number] => 16/397084 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397084 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/397084
Bit string operations using a computing tile Apr 28, 2019 Issued
Array ( [id] => 17999525 [patent_doc_number] => 11500632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Processor device for executing SIMD instructions [patent_app_type] => utility [patent_app_number] => 17/049197 [patent_app_country] => US [patent_app_date] => 2019-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5984 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17049197 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/049197
Processor device for executing SIMD instructions Apr 22, 2019 Issued
Array ( [id] => 15700855 [patent_doc_number] => 10606603 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-31 [patent_title] => Methods and apparatus for facilitating a memory mis-speculation recovery [patent_app_type] => utility [patent_app_number] => 16/378514 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15104 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378514 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/378514
Methods and apparatus for facilitating a memory mis-speculation recovery Apr 7, 2019 Issued
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