Allen Chan

Array ( [id] => 18873553 [patent_doc_number] => 11861367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Processor with variable pre-fetch threshold [patent_app_type] => utility [patent_app_number] => 17/550572 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5172 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18644729 [patent_doc_number] => 11768798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Multi-level hierarchical routing matrices for pattern-recognition processors [patent_app_type] => utility [patent_app_number] => 17/550593 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 9756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19136889 [patent_doc_number] => 11971847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Reconfigurable parallel processing [patent_app_type] => utility [patent_app_number] => 17/547668 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 30655 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20203010 [patent_doc_number] => 12405789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Load chunk instruction and store chunk instruction [patent_app_type] => utility [patent_app_number] => 18/260972 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 20991 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18260972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17613791 [patent_doc_number] => 20220156071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => VECTOR REDUCTIONS USING SHARED SCRATCHPAD MEMORY [patent_app_type] => utility [patent_app_number] => 17/530869 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17446274 [patent_doc_number] => 20220066779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => OBSOLETING VALUES STORED IN REGISTERS IN A PROCESSOR BASED ON PROCESSING OBSOLESCENT REGISTER-ENCODED INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/522517 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18348180 [patent_doc_number] => 20230136291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => ZERO EXTENDED 52-BIT INTEGER FUSED MULTIPLY ADD AND SUBTRACT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/514549 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17514549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17358643 [patent_doc_number] => 20220019439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => DATA PROCESSING APPARATUS AND RELATED PRODUCTS [patent_app_type] => utility [patent_app_number] => 17/489671 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 77564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17489671 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18756043 [patent_doc_number] => 20230359488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => CENTRAL PROCESSING UNIT WITH MULTIPLE INSTRUCTION QUEUES [patent_app_type] => utility [patent_app_number] => 18/029232 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18029232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17340281 [patent_doc_number] => 20220006612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/480117 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17316961 [patent_doc_number] => 20210406010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => PROCESSOR AND CONTROL METHOD FOR PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/447316 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19327926 [patent_doc_number] => 12045614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Streaming engine with cache-like stream data storage and lifetime tracking [patent_app_type] => utility [patent_app_number] => 17/467550 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 45 [patent_no_of_words] => 25399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19122748 [patent_doc_number] => 11966737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Robust, efficient multiprocessor-coprocessor interface [patent_app_type] => utility [patent_app_number] => 17/465234 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 42 [patent_no_of_words] => 38111 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19841572 [patent_doc_number] => 12253959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Memory protection for gather-scatter operations [patent_app_type] => utility [patent_app_number] => 18/024208 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14525 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18024208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18222624 [patent_doc_number] => 20230061618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => BFLOAT16 SQUARE ROOT AND/OR RECIPROCAL SQUARE ROOT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/463374 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17245590 [patent_doc_number] => 20210365334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => MEMORY-BASED DISTRIBUTED PROCESSOR ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/397061 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17245659 [patent_doc_number] => 20210365403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => Event Messaging in a System Having a Self-Scheduling Processor and a Hybrid Threading Fabric [patent_app_type] => utility [patent_app_number] => 17/392550 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17230799 [patent_doc_number] => 20210357356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => Multi-Threaded, Self-Scheduling Processor [patent_app_type] => utility [patent_app_number] => 17/390897 [patent_app_country] => US [patent_app_date] => 2021-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17390897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18750558 [patent_doc_number] => 11809872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Thread commencement using a work descriptor packet in a self-scheduling processor [patent_app_type] => utility [patent_app_number] => 17/384767 [patent_app_country] => US [patent_app_date] => 2021-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 25211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19669861 [patent_doc_number] => 12182621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => System and method for using sparsity to accelerate deep learning networks [patent_app_type] => utility [patent_app_number] => 18/005725 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 11784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18005725 [rel_patent_id] =>[rel_patent_doc_number] =>)