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Allison Bernstein

Examiner (ID: 3552, Phone: (571)272-9011 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1318
Issued Applications
1058
Pending Applications
79
Abandoned Applications
194

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20785683 [patent_doc_number] => 20260173891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-18 [patent_title] => ELECTROSTATIC PROTECTION OF HETEROGENEOUSLY-INTEGRATED SEMICONDUCTORS [patent_app_type] => utility [patent_app_number] => 19/420221 [patent_app_country] => US [patent_app_date] => 2025-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19420221 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/420221
ELECTROSTATIC PROTECTION OF HETEROGENEOUSLY-INTEGRATED SEMICONDUCTORS Dec 14, 2025 Pending
Array ( [id] => 20792687 [patent_doc_number] => 12666619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => 3D semiconductor devices and structures with logic and memory, and a semiconductor die [patent_app_type] => utility [patent_app_number] => 19/345854 [patent_app_country] => US [patent_app_date] => 2025-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 225 [patent_figures_cnt] => 285 [patent_no_of_words] => 38464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19345854 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/345854
3D semiconductor devices and structures with logic and memory, and a semiconductor die Sep 29, 2025 Issued
Array ( [id] => 20292930 [patent_doc_number] => 20250318173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND A POWER DELIVERY PATH [patent_app_type] => utility [patent_app_number] => 19/245349 [patent_app_country] => US [patent_app_date] => 2025-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19245349 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/245349
3D semiconductor device and structure with metal layers and a power delivery path Jun 21, 2025 Issued
Array ( [id] => 20590220 [patent_doc_number] => 20260075821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC AND MEMORY [patent_app_type] => utility [patent_app_number] => 19/243077 [patent_app_country] => US [patent_app_date] => 2025-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19243077 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/243077
3D semiconductor device and structure with logic and memory Jun 18, 2025 Issued
Array ( [id] => 19749202 [patent_doc_number] => 20250037767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => 3D MEMORY DEVICE INCLUDING SHARED SELECT GATE CONNECTIONS BETWEEN MEMORY BLOCKS [patent_app_type] => utility [patent_app_number] => 18/911523 [patent_app_country] => US [patent_app_date] => 2024-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18911523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/911523
3D MEMORY DEVICE INCLUDING SHARED SELECT GATE CONNECTIONS BETWEEN MEMORY BLOCKS Oct 9, 2024 Pending
Array ( [id] => 20791092 [patent_doc_number] => 12665008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => MRAM layout [patent_app_type] => utility [patent_app_number] => 18/798848 [patent_app_country] => US [patent_app_date] => 2024-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18798848 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/798848
MRAM layout Aug 8, 2024 Issued
Array ( [id] => 19575545 [patent_doc_number] => 20240379837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND A POWER DELIVERY PATH [patent_app_type] => utility [patent_app_number] => 18/778978 [patent_app_country] => US [patent_app_date] => 2024-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778978 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778978
3D semiconductor device and structure with metal layers and a power delivery path Jul 19, 2024 Issued
Array ( [id] => 19698430 [patent_doc_number] => 20250016975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => MEMORY DEVICE USING SEMICONDUCTOR ELEMENT [patent_app_type] => utility [patent_app_number] => 18/763737 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763737 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763737
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT Jul 2, 2024 Pending
Array ( [id] => 20463692 [patent_doc_number] => 20260013124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => MEMORY CELL AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/763861 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763861
MEMORY CELL AND METHOD FOR FABRICATING THE SAME Jul 2, 2024 Pending
Array ( [id] => 19531491 [patent_doc_number] => 20240355393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => DEVICE-REGION LAYOUT FOR EMBEDDED FLASH [patent_app_type] => utility [patent_app_number] => 18/760318 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760318
DEVICE-REGION LAYOUT FOR EMBEDDED FLASH Jun 30, 2024 Pending
Array ( [id] => 19742907 [patent_doc_number] => 12219769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => 3D semiconductor device and structure with logic and memory [patent_app_type] => utility [patent_app_number] => 18/738721 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 218 [patent_figures_cnt] => 265 [patent_no_of_words] => 38187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738721 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/738721
3D semiconductor device and structure with logic and memory Jun 9, 2024 Issued
Array ( [id] => 20792681 [patent_doc_number] => 12666613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Bit-erasable embedded select in trench memory (ESTM) [patent_app_type] => utility [patent_app_number] => 18/735967 [patent_app_country] => US [patent_app_date] => 2024-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735967 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735967
Bit-erasable embedded select in trench memory (ESTM) Jun 5, 2024 Issued
Array ( [id] => 20399114 [patent_doc_number] => 20250374589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/678783 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678783 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/678783
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF May 29, 2024 Pending
Array ( [id] => 19495842 [patent_doc_number] => 12114583 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-08 [patent_title] => Se-based selector material, selector unit and method for preparing the same [patent_app_type] => utility [patent_app_number] => 18/676385 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3394 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676385 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676385
Se-based selector material, selector unit and method for preparing the same May 27, 2024 Issued
Array ( [id] => 19454884 [patent_doc_number] => 20240315014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MIM MEMORY CELL WITH BACKSIDE INTERCONNECT STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/670472 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670472 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670472
MIM MEMORY CELL WITH BACKSIDE INTERCONNECT STRUCTURES May 20, 2024 Issued
Array ( [id] => 20367520 [patent_doc_number] => 20250357332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/664291 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664291 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664291
SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME May 14, 2024 Pending
Array ( [id] => 19868393 [patent_doc_number] => 20250107179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/663867 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663867
INTEGRATED CIRCUIT DEVICE May 13, 2024 Pending
Array ( [id] => 20124273 [patent_doc_number] => 20250239304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => MEMORY DEVICE, METHOD OF MANUFACTURING, AND INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/661000 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661000 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661000
MEMORY DEVICE, METHOD OF MANUFACTURING, AND INTEGRATED CIRCUIT DEVICE May 9, 2024 Pending
Array ( [id] => 19604983 [patent_doc_number] => 20240395863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => ONE TIME PROGRAMMING MEMORY INCLUDING FORKSHEET TRANSISTORS AND USING PHYSICALLY UNCLONABLE FUNCTION TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 18/660626 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 587 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660626 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660626
ONE TIME PROGRAMMING MEMORY INCLUDING FORKSHEET TRANSISTORS AND USING PHYSICALLY UNCLONABLE FUNCTION TECHNOLOGY May 9, 2024 Pending
Array ( [id] => 19422323 [patent_doc_number] => 20240298447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => SEMICONDUCTOR DEVICE, DRIVING METHOD OF SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/658092 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658092 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/658092
SEMICONDUCTOR DEVICE, DRIVING METHOD OF SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE May 7, 2024 Pending
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