Search

Allison Bernstein

Examiner (ID: 5744, Phone: (571)272-9011 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1280
Issued Applications
1039
Pending Applications
64
Abandoned Applications
192

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19178201 [patent_doc_number] => 20240164175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => DISPLAY APPARATUS AND METHOD FOR MANUFACTURING DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/284612 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 43109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18284612 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/284612
DISPLAY APPARATUS AND METHOD FOR MANUFACTURING DISPLAY APPARATUS Apr 7, 2022 Issued
Array ( [id] => 17854916 [patent_doc_number] => 20220284959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => MULTI-DECKS MEMORY DEVICE INCLUDING INTER-DECK SWITCHES [patent_app_type] => utility [patent_app_number] => 17/706087 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706087
Multi-decks memory device including inter-deck switches Mar 27, 2022 Issued
Array ( [id] => 17933383 [patent_doc_number] => 20220328509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => BIT-ERASABLE EMBEDDED SELECT IN TRENCH MEMORY (ESTM) [patent_app_type] => utility [patent_app_number] => 17/700323 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17700323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/700323
Bit-erasable embedded Select in Trench Memory (eSTM) Mar 20, 2022 Issued
Array ( [id] => 19907768 [patent_doc_number] => 12284798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Microelectronic devices including control logic circuitry overlying memory arrays, and related memory devices and electronic systems [patent_app_type] => utility [patent_app_number] => 17/698558 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8699 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/698558
Microelectronic devices including control logic circuitry overlying memory arrays, and related memory devices and electronic systems Mar 17, 2022 Issued
Array ( [id] => 17692340 [patent_doc_number] => 20220199633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => INTEGRATION OF A FERROELECTRIC MEMORY DEVICE WITH A TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/654521 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654521
Integration of a ferroelectric memory device with a transistor Mar 10, 2022 Issued
Array ( [id] => 17676869 [patent_doc_number] => 20220190036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => MULTI-LAYERED CONDUCTIVE METAL OXIDE STRUCTURES AND METHODS FOR FACILITATING ENHANCED PERFORMANCE CHARACTERISTICS OF TWO-TERMINAL MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/687900 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17687900 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/687900
Multi-layered conductive metal oxide structures and methods for facilitating enhanced performance characteristics of two-terminal memory cells Mar 6, 2022 Issued
Array ( [id] => 17752834 [patent_doc_number] => 20220231039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING STACK STRUCTURE HAVING GATE REGION AND INSULATING REGION [patent_app_type] => utility [patent_app_number] => 17/685692 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685692 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685692
Semiconductor devices including stack structure having gate region and insulating region Mar 2, 2022 Issued
Array ( [id] => 19626890 [patent_doc_number] => 12165737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Multi-bitcell structure with shared read port [patent_app_type] => utility [patent_app_number] => 17/684894 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17684894 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/684894
Multi-bitcell structure with shared read port Mar 1, 2022 Issued
Array ( [id] => 18601834 [patent_doc_number] => 20230276639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => METAL SILICIDE LAYER FOR MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/682907 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682907
METAL SILICIDE LAYER FOR MEMORY ARRAY Feb 27, 2022 Pending
Array ( [id] => 19200673 [patent_doc_number] => 11997937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Chalcogenide memory device compositions [patent_app_type] => utility [patent_app_number] => 17/676708 [patent_app_country] => US [patent_app_date] => 2022-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 14107 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676708 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/676708
Chalcogenide memory device compositions Feb 20, 2022 Issued
Array ( [id] => 18595153 [patent_doc_number] => 11744075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Semiconductor memory device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/672819 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 82 [patent_no_of_words] => 12275 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672819 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/672819
Semiconductor memory device and method for manufacturing the same Feb 15, 2022 Issued
Array ( [id] => 18317612 [patent_doc_number] => 11631697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Integrated assemblies having vertically-extending channel material with alternating regions of different dopant distributions, and methods of forming integrated assemblies [patent_app_type] => utility [patent_app_number] => 17/672659 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 34 [patent_no_of_words] => 8895 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672659 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/672659
Integrated assemblies having vertically-extending channel material with alternating regions of different dopant distributions, and methods of forming integrated assemblies Feb 14, 2022 Issued
Array ( [id] => 19828838 [patent_doc_number] => 12249634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Vertical-conduction silicon carbide MOSFET device having improved gate biasing structure and manufacturing process thereof [patent_app_type] => utility [patent_app_number] => 17/669239 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 7387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669239 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/669239
Vertical-conduction silicon carbide MOSFET device having improved gate biasing structure and manufacturing process thereof Feb 9, 2022 Issued
Array ( [id] => 19681354 [patent_doc_number] => 12193243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Lateral multi-bit memory devices and methods of making the same [patent_app_type] => utility [patent_app_number] => 17/650084 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 10486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650084 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650084
Lateral multi-bit memory devices and methods of making the same Feb 6, 2022 Issued
Array ( [id] => 18364762 [patent_doc_number] => 20230146353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/665560 [patent_app_country] => US [patent_app_date] => 2022-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665560 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665560
3D semiconductor device and structure with logic and memory Feb 5, 2022 Issued
Array ( [id] => 18251746 [patent_doc_number] => 20230078785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/582990 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582990 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582990
Semiconductor device Jan 23, 2022 Issued
Array ( [id] => 17752711 [patent_doc_number] => 20220230916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/648541 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648541 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648541
Semiconductor structure and manufacturing method thereof Jan 19, 2022 Issued
Array ( [id] => 17764775 [patent_doc_number] => 20220238388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => METHOD OF PRODUCING A GATE CUT IN A SEMICONDUCTOR COMPONENT [patent_app_type] => utility [patent_app_number] => 17/580020 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580020 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580020
Method of producing a gate cut in a semiconductor component Jan 19, 2022 Issued
Array ( [id] => 17638236 [patent_doc_number] => 11348972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-31 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/648214 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5457 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648214 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648214
Semiconductor structure and manufacturing method thereof Jan 17, 2022 Issued
Array ( [id] => 18394973 [patent_doc_number] => 20230163194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => Dummy Hybrid Film for Self-Alignment Contact Formation [patent_app_type] => utility [patent_app_number] => 17/648037 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648037
Dummy hybrid film for self-alignment contact formation Jan 13, 2022 Issued
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