
Allison Bernstein
Examiner (ID: 3552, Phone: (571)272-9011 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824 |
| Total Applications | 1318 |
| Issued Applications | 1058 |
| Pending Applications | 79 |
| Abandoned Applications | 194 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19626890
[patent_doc_number] => 12165737
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-10
[patent_title] => Multi-bitcell structure with shared read port
[patent_app_type] => utility
[patent_app_number] => 17/684894
[patent_app_country] => US
[patent_app_date] => 2022-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 7818
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17684894
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/684894 | Multi-bitcell structure with shared read port | Mar 1, 2022 | Issued |
Array
(
[id] => 18601834
[patent_doc_number] => 20230276639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-31
[patent_title] => METAL SILICIDE LAYER FOR MEMORY ARRAY
[patent_app_type] => utility
[patent_app_number] => 17/682907
[patent_app_country] => US
[patent_app_date] => 2022-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14020
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 33
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682907
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/682907 | METAL SILICIDE LAYER FOR MEMORY ARRAY | Feb 27, 2022 | Pending |
Array
(
[id] => 19200673
[patent_doc_number] => 11997937
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-28
[patent_title] => Chalcogenide memory device compositions
[patent_app_type] => utility
[patent_app_number] => 17/676708
[patent_app_country] => US
[patent_app_date] => 2022-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 14107
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676708
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/676708 | Chalcogenide memory device compositions | Feb 20, 2022 | Issued |
Array
(
[id] => 18595153
[patent_doc_number] => 11744075
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-29
[patent_title] => Semiconductor memory device and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/672819
[patent_app_country] => US
[patent_app_date] => 2022-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 82
[patent_no_of_words] => 12275
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672819
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/672819 | Semiconductor memory device and method for manufacturing the same | Feb 15, 2022 | Issued |
Array
(
[id] => 18317612
[patent_doc_number] => 11631697
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-18
[patent_title] => Integrated assemblies having vertically-extending channel material with alternating regions of different dopant distributions, and methods of forming integrated assemblies
[patent_app_type] => utility
[patent_app_number] => 17/672659
[patent_app_country] => US
[patent_app_date] => 2022-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 34
[patent_no_of_words] => 8895
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672659
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/672659 | Integrated assemblies having vertically-extending channel material with alternating regions of different dopant distributions, and methods of forming integrated assemblies | Feb 14, 2022 | Issued |
Array
(
[id] => 19828838
[patent_doc_number] => 12249634
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-11
[patent_title] => Vertical-conduction silicon carbide MOSFET device having improved gate biasing structure and manufacturing process thereof
[patent_app_type] => utility
[patent_app_number] => 17/669239
[patent_app_country] => US
[patent_app_date] => 2022-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 7387
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669239
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/669239 | Vertical-conduction silicon carbide MOSFET device having improved gate biasing structure and manufacturing process thereof | Feb 9, 2022 | Issued |
Array
(
[id] => 19681354
[patent_doc_number] => 12193243
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-07
[patent_title] => Lateral multi-bit memory devices and methods of making the same
[patent_app_type] => utility
[patent_app_number] => 17/650084
[patent_app_country] => US
[patent_app_date] => 2022-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 27
[patent_no_of_words] => 10486
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650084
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/650084 | Lateral multi-bit memory devices and methods of making the same | Feb 6, 2022 | Issued |
Array
(
[id] => 18364762
[patent_doc_number] => 20230146353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-11
[patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC AND MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/665560
[patent_app_country] => US
[patent_app_date] => 2022-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 35887
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665560
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/665560 | 3D semiconductor device and structure with logic and memory | Feb 5, 2022 | Issued |
Array
(
[id] => 18251746
[patent_doc_number] => 20230078785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-16
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/582990
[patent_app_country] => US
[patent_app_date] => 2022-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6862
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 348
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582990
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/582990 | Semiconductor device | Jan 23, 2022 | Issued |
Array
(
[id] => 17764775
[patent_doc_number] => 20220238388
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-28
[patent_title] => METHOD OF PRODUCING A GATE CUT IN A SEMICONDUCTOR COMPONENT
[patent_app_type] => utility
[patent_app_number] => 17/580020
[patent_app_country] => US
[patent_app_date] => 2022-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6576
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580020
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/580020 | Method of producing a gate cut in a semiconductor component | Jan 19, 2022 | Issued |
Array
(
[id] => 17752711
[patent_doc_number] => 20220230916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-21
[patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/648541
[patent_app_country] => US
[patent_app_date] => 2022-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7452
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648541
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/648541 | Semiconductor structure and manufacturing method thereof | Jan 19, 2022 | Issued |
Array
(
[id] => 17638236
[patent_doc_number] => 11348972
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-05-31
[patent_title] => Semiconductor structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/648214
[patent_app_country] => US
[patent_app_date] => 2022-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5457
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648214
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/648214 | Semiconductor structure and manufacturing method thereof | Jan 17, 2022 | Issued |
Array
(
[id] => 18394973
[patent_doc_number] => 20230163194
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-25
[patent_title] => Dummy Hybrid Film for Self-Alignment Contact Formation
[patent_app_type] => utility
[patent_app_number] => 17/648037
[patent_app_country] => US
[patent_app_date] => 2022-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6673
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648037
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/648037 | Dummy hybrid film for self-alignment contact formation | Jan 13, 2022 | Issued |
Array
(
[id] => 18131381
[patent_doc_number] => 11557598
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Non-volatile memory and forming method thereof
[patent_app_type] => utility
[patent_app_number] => 17/573578
[patent_app_country] => US
[patent_app_date] => 2022-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2921
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573578
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/573578 | Non-volatile memory and forming method thereof | Jan 10, 2022 | Issued |
Array
(
[id] => 18500671
[patent_doc_number] => 20230223467
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-13
[patent_title] => HIGH ELECTRON MOBILITY TRANSISTORS (HEMTS) INCLUDING A YTTRIUM (Y) AND ALUMINUM NITRIDE (AlN) (YAlN) ALLOY LAYER
[patent_app_type] => utility
[patent_app_number] => 17/570600
[patent_app_country] => US
[patent_app_date] => 2022-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4824
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570600
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/570600 | High electron mobility transistors (HEMTS) including a yttrium (Y) and aluminum nitride (AIN) (YAIN) alloy layer | Jan 6, 2022 | Issued |
Array
(
[id] => 18475738
[patent_doc_number] => 20230210026
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => COMPOSITE MATERIAL PHASE CHANGE MEMORY CELL
[patent_app_type] => utility
[patent_app_number] => 17/646210
[patent_app_country] => US
[patent_app_date] => 2021-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6058
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646210
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/646210 | Composite material phase change memory cell | Dec 27, 2021 | Issued |
Array
(
[id] => 19294321
[patent_doc_number] => 12033682
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => In-plane magnetized spin-orbit magnetic device
[patent_app_type] => utility
[patent_app_number] => 17/563100
[patent_app_country] => US
[patent_app_date] => 2021-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6430
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563100
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/563100 | In-plane magnetized spin-orbit magnetic device | Dec 27, 2021 | Issued |
Array
(
[id] => 18475544
[patent_doc_number] => 20230209832
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => THREE-DIMENSIONAL MEMORY DEVICE INCLUDING SENSE AMPLIFIERS HAVING A COMMON WIDTH AND SEPARATION
[patent_app_type] => utility
[patent_app_number] => 17/562248
[patent_app_country] => US
[patent_app_date] => 2021-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12764
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562248
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/562248 | Three-dimensional memory device including sense amplifiers having a common width and separation | Dec 26, 2021 | Issued |
Array
(
[id] => 18458802
[patent_doc_number] => 20230200084
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-22
[patent_title] => DIAGONAL MEMORY WITH VERTICAL TRANSISTORS AND WRAP-AROUND CONTROL LINES
[patent_app_type] => utility
[patent_app_number] => 17/558688
[patent_app_country] => US
[patent_app_date] => 2021-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25333
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558688
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/558688 | Diagonal memory with vertical transistors and wrap-around control lines | Dec 21, 2021 | Issued |
Array
(
[id] => 18458798
[patent_doc_number] => 20230200080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-22
[patent_title] => 3D FERROELECTRIC MEMORY CELL ARCHITECTURES
[patent_app_type] => utility
[patent_app_number] => 17/558419
[patent_app_country] => US
[patent_app_date] => 2021-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13478
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558419
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/558419 | 3D FERROELECTRIC MEMORY CELL ARCHITECTURES | Dec 20, 2021 | Pending |