Search

Allison Bernstein

Examiner (ID: 3552, Phone: (571)272-9011 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1318
Issued Applications
1058
Pending Applications
79
Abandoned Applications
194

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19394792 [patent_doc_number] => 20240284662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/435231 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435231 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435231
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME Feb 6, 2024 Pending
Array ( [id] => 19364286 [patent_doc_number] => 20240266320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => METHOD OF INTERCONNECTING SEMICONDUCTOR DEVICES AND ASSEMBLY OF INTERCONNECTED SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/434566 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434566 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/434566
METHOD OF INTERCONNECTING SEMICONDUCTOR DEVICES AND ASSEMBLY OF INTERCONNECTED SEMICONDUCTOR DEVICES Feb 5, 2024 Pending
Array ( [id] => 19444673 [patent_doc_number] => 12094965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => 3D semiconductor device and structure with metal layers and memory cells [patent_app_type] => utility [patent_app_number] => 18/429202 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 125 [patent_figures_cnt] => 146 [patent_no_of_words] => 31980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429202
3D semiconductor device and structure with metal layers and memory cells Jan 30, 2024 Issued
Array ( [id] => 19349296 [patent_doc_number] => 20240258260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR PACKAGING METHOD AND THE STRUCTURE FORMED THEREFROM [patent_app_type] => utility [patent_app_number] => 18/422034 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18422034 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/422034
SEMICONDUCTOR PACKAGING METHOD AND THE STRUCTURE FORMED THEREFROM Jan 24, 2024 Pending
Array ( [id] => 19662111 [patent_doc_number] => 20240429176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/417494 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417494 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/417494
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Jan 18, 2024 Pending
Array ( [id] => 19146360 [patent_doc_number] => 20240145390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/410874 [patent_app_country] => US [patent_app_date] => 2024-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18410874 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/410874
Semiconductor integrated circuit device Jan 10, 2024 Issued
Array ( [id] => 19591837 [patent_doc_number] => 20240389394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => DISPLAY DEVICE AND METHOD FOR PROVIDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/410134 [patent_app_country] => US [patent_app_date] => 2024-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18410134 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/410134
DISPLAY DEVICE AND METHOD FOR PROVIDING THE SAME Jan 10, 2024 Pending
Array ( [id] => 19604962 [patent_doc_number] => 20240395842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/406918 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406918
IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME Jan 7, 2024 Pending
Array ( [id] => 19335342 [patent_doc_number] => 20240249772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => ELONGATED CAPACITORS IN 3D NAND MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/405049 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18405049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/405049
ELONGATED CAPACITORS IN 3D NAND MEMORY DEVICES Jan 4, 2024 Pending
Array ( [id] => 19239569 [patent_doc_number] => 20240196765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MEMORY DEVICE WITH LATERALLY FORMED MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/545636 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545636 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/545636
MEMORY DEVICE WITH LATERALLY FORMED MEMORY CELLS Dec 18, 2023 Pending
Array ( [id] => 19509439 [patent_doc_number] => 12120880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-15 [patent_title] => 3D semiconductor device and structure with logic and memory [patent_app_type] => utility [patent_app_number] => 18/527356 [patent_app_country] => US [patent_app_date] => 2023-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 218 [patent_figures_cnt] => 275 [patent_no_of_words] => 37583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527356 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527356
3D semiconductor device and structure with logic and memory Dec 2, 2023 Issued
Array ( [id] => 19803752 [patent_doc_number] => 20250069677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/526278 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526278 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/526278
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Nov 30, 2023 Pending
Array ( [id] => 19057019 [patent_doc_number] => 20240098988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => INTEGRATED CIRCUIT WITH BACK-SIDE METAL LINE, METHOD OF FABRICATING THE SAME, AND LAYOUT METHOD [patent_app_type] => utility [patent_app_number] => 18/521375 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521375 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521375
INTEGRATED CIRCUIT WITH BACK-SIDE METAL LINE, METHOD OF FABRICATING THE SAME, AND LAYOUT METHOD Nov 27, 2023 Pending
Array ( [id] => 19296154 [patent_doc_number] => 12035531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => 3D semiconductor device and structure with logic and memory [patent_app_type] => utility [patent_app_number] => 18/516958 [patent_app_country] => US [patent_app_date] => 2023-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 218 [patent_figures_cnt] => 266 [patent_no_of_words] => 36957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516958 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/516958
3D semiconductor device and structure with logic and memory Nov 21, 2023 Issued
Array ( [id] => 19040395 [patent_doc_number] => 20240090210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICES WITH DIFFERENT DOPING TYPES [patent_app_type] => utility [patent_app_number] => 18/518142 [patent_app_country] => US [patent_app_date] => 2023-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9986 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518142 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518142
Semiconductor memory devices with different doping types Nov 21, 2023 Issued
Array ( [id] => 19185266 [patent_doc_number] => 11991884 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-21 [patent_title] => 3D semiconductor device and structure with logic and memory [patent_app_type] => utility [patent_app_number] => 18/515255 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 218 [patent_figures_cnt] => 264 [patent_no_of_words] => 36394 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515255 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515255
3D semiconductor device and structure with logic and memory Nov 20, 2023 Issued
Array ( [id] => 20019698 [patent_doc_number] => 20250157920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => MESHED TRANSMISSION LINE [patent_app_type] => utility [patent_app_number] => 18/510319 [patent_app_country] => US [patent_app_date] => 2023-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18510319 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/510319
MESHED TRANSMISSION LINE Nov 14, 2023 Pending
Array ( [id] => 19046829 [patent_doc_number] => 11935949 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-19 [patent_title] => 3D semiconductor device and structure with metal layers and memory cells [patent_app_type] => utility [patent_app_number] => 18/388852 [patent_app_country] => US [patent_app_date] => 2023-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 125 [patent_figures_cnt] => 146 [patent_no_of_words] => 31921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18388852 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/388852
3D semiconductor device and structure with metal layers and memory cells Nov 11, 2023 Issued
Array ( [id] => 20734504 [patent_doc_number] => 12641769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Integrated circuit, system and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/498350 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 18677 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18498350 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/498350
Integrated circuit, system and method of forming the same Oct 30, 2023 Issued
Array ( [id] => 19573573 [patent_doc_number] => 20240377865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => MEMORY DEVICE HAVING A SUPPORT STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/489705 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489705 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489705
Memory device having a support structure Oct 17, 2023 Issued
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