Search

Allison Bernstein

Examiner (ID: 3552, Phone: (571)272-9011 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
1318
Issued Applications
1058
Pending Applications
79
Abandoned Applications
194

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18945641 [patent_doc_number] => 20240040780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => SEMICONDUCTOR DEVICE WITH PROGRAMMABLE UNIT AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/377418 [patent_app_country] => US [patent_app_date] => 2023-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18377418 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/377418
Semiconductor device with programmable unit and method for fabricating the same Oct 5, 2023 Issued
Array ( [id] => 18900473 [patent_doc_number] => 20240015958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => ONE-TIME PROGRAMMABLE MEMORY STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/470447 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470447 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/470447
One-time programmable memory structure Sep 19, 2023 Issued
Array ( [id] => 20691810 [patent_doc_number] => 12621981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/369552 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 2363 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18369552 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/369552
Semiconductor memory device Sep 17, 2023 Issued
Array ( [id] => 19531834 [patent_doc_number] => 20240355736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF, MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/463266 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18463266 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/463266
SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF, MEMORY DEVICE AND MEMORY SYSTEM Sep 6, 2023 Pending
Array ( [id] => 19024909 [patent_doc_number] => 20240081080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => FERROELECTRIC SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/461266 [patent_app_country] => US [patent_app_date] => 2023-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18461266 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/461266
FERROELECTRIC SEMICONDUCTOR DEVICE Sep 4, 2023 Pending
Array ( [id] => 19806180 [patent_doc_number] => 20250072105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => VERTICAL STRUCTURE-BASED FIELD EFFECT TRANSISTOR (FET) INPUT/OUTPUT DEVICE INTEGRATION [patent_app_type] => utility [patent_app_number] => 18/455511 [patent_app_country] => US [patent_app_date] => 2023-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455511 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/455511
VERTICAL STRUCTURE-BASED FIELD EFFECT TRANSISTOR (FET) INPUT/OUTPUT DEVICE INTEGRATION Aug 23, 2023 Abandoned
Array ( [id] => 20483996 [patent_doc_number] => 12532475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Memory device with through-stack contact via structures which contact plural stacks and method of making the same [patent_app_type] => utility [patent_app_number] => 18/455079 [patent_app_country] => US [patent_app_date] => 2023-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 19636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/455079
Memory device with through-stack contact via structures which contact plural stacks and method of making the same Aug 23, 2023 Issued
Array ( [id] => 19335705 [patent_doc_number] => 20240250135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/454112 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18454112 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/454112
INTEGRATED CIRCUIT DEVICE Aug 22, 2023 Issued
Array ( [id] => 18898351 [patent_doc_number] => 20240013836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => PREVENTION OF FLOATING GATE 3D-NAND CELL RESIDUAL BY USING HYBRID PLUG PROCESS IN SUPER-DECK STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/237077 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18237077 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/237077
PREVENTION OF FLOATING GATE 3D-NAND CELL RESIDUAL BY USING HYBRID PLUG PROCESS IN SUPER-DECK STRUCTURE Aug 22, 2023 Pending
Array ( [id] => 20885639 [patent_doc_number] => 12701697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-04 [patent_title] => Integrated circuit device, memory device, and method of manufacturing [patent_app_type] => utility [patent_app_number] => 18/452973 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 13521 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18452973 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/452973
INTEGRATED CIRCUIT DEVICE, MEMORY DEVICE, AND METHOD OF MANUFACTURING Aug 20, 2023 Pending
Array ( [id] => 18820796 [patent_doc_number] => 20230395137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => Memory Device Comprising An Electrically Floating Body Transistor [patent_app_type] => utility [patent_app_number] => 18/233985 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18233985 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/233985
Memory device comprising an electrically floating body transistor Aug 14, 2023 Issued
Array ( [id] => 19057049 [patent_doc_number] => 20240099018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => INTEGRATION OF FERROELECTRIC MEMORY DEVICES HAVING STACKED ELECTRODES WITH TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/357974 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357974
Integration of ferroelectric memory devices having stacked electrodes with transistors Aug 14, 2023 Issued
Array ( [id] => 20191155 [patent_doc_number] => 12402293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Stacked SRAM cell architecture [patent_app_type] => utility [patent_app_number] => 18/448607 [patent_app_country] => US [patent_app_date] => 2023-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 55 [patent_no_of_words] => 16689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 401 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448607 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448607
Stacked SRAM cell architecture Aug 10, 2023 Issued
Array ( [id] => 19690305 [patent_doc_number] => 20250008850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => Resistive random access memory structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/232362 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232362 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/232362
Resistive random access memory structure and manufacturing method thereof Aug 9, 2023 Issued
Array ( [id] => 19500117 [patent_doc_number] => 20240339135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/365726 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365726 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365726
Semiconductor device and method of manufacturing semiconductor device Aug 3, 2023 Issued
Array ( [id] => 18791197 [patent_doc_number] => 20230380193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MEMORY DEVICES INCLUDING STRINGS OF MEMORY CELLS AND RELATED SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/365850 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365850 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365850
Memory devices including strings of memory cells and related systems Aug 3, 2023 Issued
Array ( [id] => 20268819 [patent_doc_number] => 12439836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Semiconductor memory devices with electrically isolated stacked bit lines and methods of manufacture [patent_app_type] => utility [patent_app_number] => 18/363500 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 67 [patent_no_of_words] => 7754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363500 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363500
Semiconductor memory devices with electrically isolated stacked bit lines and methods of manufacture Jul 31, 2023 Issued
Array ( [id] => 19875208 [patent_doc_number] => 12268096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Spacer stack for magnetic tunnel junctions [patent_app_type] => utility [patent_app_number] => 18/228282 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228282 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228282
Spacer stack for magnetic tunnel junctions Jul 30, 2023 Issued
Array ( [id] => 20774538 [patent_doc_number] => 12658217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Wafer-on-wafer memory device architectures [patent_app_type] => utility [patent_app_number] => 18/228148 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228148 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228148
Wafer-on-wafer memory device architectures Jul 30, 2023 Issued
Array ( [id] => 18891186 [patent_doc_number] => 11869965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => 3D semiconductor device and structure with metal layers and memory cells [patent_app_type] => utility [patent_app_number] => 18/227183 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 125 [patent_figures_cnt] => 146 [patent_no_of_words] => 31841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227183 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/227183
3D semiconductor device and structure with metal layers and memory cells Jul 26, 2023 Issued
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