Search

Alonzo Chambliss

Examiner (ID: 7113, Phone: (571)272-1927 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2814, 2827, 2892, 2897
Total Applications
2434
Issued Applications
2138
Pending Applications
110
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20560161 [patent_doc_number] => 20260059951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-26 [patent_title] => DISPLAY INCLUDING STRUCTURE FOR PROVIDING DIFFERENT STATES FOR DISPLAYING SCREEN, AND ELECTRONIC DEVICE INCLUDING SAME [patent_app_type] => utility [patent_app_number] => 19/377661 [patent_app_country] => US [patent_app_date] => 2025-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19377661 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/377661
DISPLAY INCLUDING STRUCTURE FOR PROVIDING DIFFERENT STATES FOR DISPLAYING SCREEN, AND ELECTRONIC DEVICE INCLUDING SAME Nov 2, 2025 Pending
Array ( [id] => 20574846 [patent_doc_number] => 20260068780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => PACKAGE COMPRISING DUMMY SILICON STRUCTURE LOCATED BETWEEN INTEGRATED DEVICES [patent_app_type] => utility [patent_app_number] => 19/378139 [patent_app_country] => US [patent_app_date] => 2025-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19378139 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/378139
PACKAGE COMPRISING DUMMY SILICON STRUCTURE LOCATED BETWEEN INTEGRATED DEVICES Nov 2, 2025 Pending
Array ( [id] => 20462276 [patent_doc_number] => 20260011705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 19/328034 [patent_app_country] => US [patent_app_date] => 2025-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19328034 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/328034
Electrical interconnects for packages containing photonic integrated circuits Sep 11, 2025 Issued
Array ( [id] => 20429641 [patent_doc_number] => 20250391734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => SEMICONDUCTOR CIRCUIT STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 19/308968 [patent_app_country] => US [patent_app_date] => 2025-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19308968 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/308968
SEMICONDUCTOR CIRCUIT STRUCTURE AND METHOD FOR FORMING THE SAME Aug 24, 2025 Pending
Array ( [id] => 20503500 [patent_doc_number] => 20260032965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => THIN-FILM TRANSISTORS AND RELATED METHODS OF MANUFACTURE WITH METAL NITRIDE SOURCE/DRAIN [patent_app_type] => utility [patent_app_number] => 19/261813 [patent_app_country] => US [patent_app_date] => 2025-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19261813 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/261813
Thin-film transistors having a metal nitride source material and related methods Jul 6, 2025 Issued
Array ( [id] => 20754947 [patent_doc_number] => 20260157181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-04 [patent_title] => BAFFLES FOR ELECTRONIC CIRCUITS IMMERSED IN COOLING FLUID IN A TANK [patent_app_type] => utility [patent_app_number] => 19/201278 [patent_app_country] => US [patent_app_date] => 2025-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19201278 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/201278
Baffles for electronic circuits immersed in cooling fluid in a tank May 6, 2025 Issued
Array ( [id] => 20036320 [patent_doc_number] => 20250174542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => SEMICONDUCTOR ASSEMBLY COMPRISING A 3D BLOCK AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 19/030747 [patent_app_country] => US [patent_app_date] => 2025-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10017 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19030747 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/030747
Semiconductor assembly comprising a 3D block and method of making the same Jan 16, 2025 Issued
Array ( [id] => 19951305 [patent_doc_number] => 12322676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-03 [patent_title] => Baffles for electronic circuits immersed in cooling fluid in a tank [patent_app_type] => utility [patent_app_number] => 18/967181 [patent_app_country] => US [patent_app_date] => 2024-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 6811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18967181 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/967181
Baffles for electronic circuits immersed in cooling fluid in a tank Dec 2, 2024 Issued
Array ( [id] => 20691946 [patent_doc_number] => 12622119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Heat dissipation structure for LED light [patent_app_type] => utility [patent_app_number] => 18/895375 [patent_app_country] => US [patent_app_date] => 2024-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1253 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18895375 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/895375
Heat dissipation structure for LED light Sep 23, 2024 Issued
Array ( [id] => 19790171 [patent_doc_number] => 20250063850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => PRODUCT, SYSTEM, AND METHOD WITH SILVER NANOSTRUCTURES THIN FILM FOR INFRARED PHOTODETECTOR [patent_app_type] => utility [patent_app_number] => 18/804273 [patent_app_country] => US [patent_app_date] => 2024-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18804273 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/804273
PRODUCT, SYSTEM, AND METHOD WITH SILVER NANOSTRUCTURES THIN FILM FOR INFRARED PHOTODETECTOR Aug 13, 2024 Pending
Array ( [id] => 19559991 [patent_doc_number] => 20240371783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEMICONDUCTOR DEVICE WITH CURVED CONDUCTIVE LINES AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/778258 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778258 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778258
SEMICONDUCTOR DEVICE WITH CURVED CONDUCTIVE LINES AND METHOD OF FORMING THE SAME Jul 18, 2024 Pending
Array ( [id] => 19559951 [patent_doc_number] => 20240371743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/777464 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18777464 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/777464
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Jul 17, 2024 Pending
Array ( [id] => 19559946 [patent_doc_number] => 20240371738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/774478 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774478 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/774478
SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES Jul 15, 2024 Pending
Array ( [id] => 19531796 [patent_doc_number] => 20240355698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => MANUFACTURING METHOD OF SENSING DIE ENCAPSULATED BY ENCAPSULANT WITH ROUGHNESS SURFACE HAVING HOLLOW REGION [patent_app_type] => utility [patent_app_number] => 18/762656 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762656
Fabricating a sensing component encapsulated by an encapsulation layer with roughed surface having a hollow region Jul 2, 2024 Issued
Array ( [id] => 20496929 [patent_doc_number] => 12538823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Power delivery for embedded bridge die utilizing trench structures [patent_app_type] => utility [patent_app_number] => 18/759008 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 1094 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759008
Power delivery for embedded bridge die utilizing trench structures Jun 27, 2024 Issued
Array ( [id] => 19868579 [patent_doc_number] => 20250107365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/753973 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753973 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753973
ELECTRONIC DEVICE Jun 24, 2024 Pending
Array ( [id] => 20089098 [patent_doc_number] => 20250219034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/751021 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751021 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/751021
Electrical interconnects for packages containing photonic integrated circuits Jun 20, 2024 Issued
Array ( [id] => 19496894 [patent_doc_number] => 20240335912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => METHOD OF FORMING A LAYER STRUCTURE, CHIP PACKAGE AND CHIP ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 18/750260 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750260 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/750260
Method of forming an intermetallic phase layer with a plurality of nickel particles Jun 20, 2024 Issued
Array ( [id] => 20089031 [patent_doc_number] => 20250218967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/751105 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751105 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/751105
Electrical interconnects for packages containing photonic integrated circuits Jun 20, 2024 Issued
Array ( [id] => 20429662 [patent_doc_number] => 20250391755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => PACKAGE COMPRISING DUMMY SILICON STRUCTURE LOCATED BETWEEN INTEGRATED DEVICES [patent_app_type] => utility [patent_app_number] => 18/748011 [patent_app_country] => US [patent_app_date] => 2024-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748011 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/748011
PACKAGE COMPRISING DUMMY SILICON STRUCTURE LOCATED BETWEEN INTEGRATED DEVICES Jun 18, 2024 Pending
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