
Alonzo Chambliss
Examiner (ID: 15572)
| Most Active Art Unit | 2897 |
| Art Unit(s) | 2897, 2827, 2814, 2892 |
| Total Applications | 2378 |
| Issued Applications | 2104 |
| Pending Applications | 102 |
| Abandoned Applications | 209 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20036320
[patent_doc_number] => 20250174542
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-29
[patent_title] => SEMICONDUCTOR ASSEMBLY COMPRISING A 3D BLOCK AND METHOD OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 19/030747
[patent_app_country] => US
[patent_app_date] => 2025-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10017
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19030747
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/030747 | Semiconductor assembly comprising a 3D block and method of making the same | Jan 16, 2025 | Issued |
Array
(
[id] => 19951305
[patent_doc_number] => 12322676
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2025-06-03
[patent_title] => Baffles for electronic circuits immersed in cooling fluid in a tank
[patent_app_type] => utility
[patent_app_number] => 18/967181
[patent_app_country] => US
[patent_app_date] => 2024-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 6811
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18967181
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/967181 | Baffles for electronic circuits immersed in cooling fluid in a tank | Dec 2, 2024 | Issued |
Array
(
[id] => 19531796
[patent_doc_number] => 20240355698
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => MANUFACTURING METHOD OF SENSING DIE ENCAPSULATED BY ENCAPSULANT WITH ROUGHNESS SURFACE HAVING HOLLOW REGION
[patent_app_type] => utility
[patent_app_number] => 18/762656
[patent_app_country] => US
[patent_app_date] => 2024-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10979
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762656
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/762656 | Fabricating a sensing component encapsulated by an encapsulation layer with roughed surface having a hollow region | Jul 2, 2024 | Issued |
Array
(
[id] => 19531843
[patent_doc_number] => 20240355745
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => POWER DELIVERY FOR EMBEDDED BRIDGE DIE UTILIZING TRENCH STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 18/759008
[patent_app_country] => US
[patent_app_date] => 2024-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6421
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759008
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/759008 | POWER DELIVERY FOR EMBEDDED BRIDGE DIE UTILIZING TRENCH STRUCTURES | Jun 27, 2024 | Pending |
Array
(
[id] => 20089098
[patent_doc_number] => 20250219034
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-03
[patent_title] => ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 18/751021
[patent_app_country] => US
[patent_app_date] => 2024-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12974
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -31
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751021
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/751021 | Electrical interconnects for packages containing photonic integrated circuits | Jun 20, 2024 | Issued |
Array
(
[id] => 19496894
[patent_doc_number] => 20240335912
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => METHOD OF FORMING A LAYER STRUCTURE, CHIP PACKAGE AND CHIP ARRANGEMENT
[patent_app_type] => utility
[patent_app_number] => 18/750260
[patent_app_country] => US
[patent_app_date] => 2024-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11585
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750260
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/750260 | Method of forming an intermetallic phase layer with a plurality of nickel particles | Jun 20, 2024 | Issued |
Array
(
[id] => 20089031
[patent_doc_number] => 20250218967
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-03
[patent_title] => ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 18/751105
[patent_app_country] => US
[patent_app_date] => 2024-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12974
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751105
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/751105 | Electrical interconnects for packages containing photonic integrated circuits | Jun 20, 2024 | Issued |
Array
(
[id] => 20274891
[patent_doc_number] => 12444676
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => Self-aligned via for interconnect structure
[patent_app_type] => utility
[patent_app_number] => 18/745773
[patent_app_country] => US
[patent_app_date] => 2024-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 1150
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745773
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/745773 | Self-aligned via for interconnect structure | Jun 16, 2024 | Issued |
Array
(
[id] => 19484070
[patent_doc_number] => 20240332112
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => CHIP-SCALE PACKAGE ARCHITECTURES CONTAINING A DIE BACK SIDE METAL AND A SOLDER THERMAL INTERFACE MATERIAL
[patent_app_type] => utility
[patent_app_number] => 18/744108
[patent_app_country] => US
[patent_app_date] => 2024-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9073
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744108
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/744108 | CHIP-SCALE PACKAGE ARCHITECTURES CONTAINING A DIE BACK SIDE METAL AND A SOLDER THERMAL INTERFACE MATERIAL | Jun 13, 2024 | Pending |
Array
(
[id] => 19646532
[patent_doc_number] => 20240421052
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => MULTI-CHIP OR MULTI-CHIPLET FAN-OUT DEVICE FOR LAMINATE AND LEADFRAME PACKAGES
[patent_app_type] => utility
[patent_app_number] => 18/742517
[patent_app_country] => US
[patent_app_date] => 2024-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15623
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742517
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/742517 | Multi-chip or multi-chiplet fan-out device for laminate and leadframe packages | Jun 12, 2024 | Issued |
Array
(
[id] => 19468126
[patent_doc_number] => 20240321796
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => PACKAGE STRUCTURE INCLUDING STACKED PILLAR PORTIONS AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/735126
[patent_app_country] => US
[patent_app_date] => 2024-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6776
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735126
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/735126 | Package structure including stacked pillar portions and method for fabricating the same | Jun 4, 2024 | Issued |
Array
(
[id] => 20305436
[patent_doc_number] => 12451436
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-21
[patent_title] => Interconnecting a plurality of dies having spare input/output circuit
[patent_app_type] => utility
[patent_app_number] => 18/671478
[patent_app_country] => US
[patent_app_date] => 2024-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 26
[patent_no_of_words] => 3376
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671478
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/671478 | Interconnecting a plurality of dies having spare input/output circuit | May 21, 2024 | Issued |
Array
(
[id] => 19394934
[patent_doc_number] => 20240284804
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => METHOD OF MANUFACTURING A MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM)
[patent_app_type] => utility
[patent_app_number] => 18/642280
[patent_app_country] => US
[patent_app_date] => 2024-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5276
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642280
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/642280 | METHOD OF MANUFACTURING A MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) | Apr 21, 2024 | Abandoned |
Array
(
[id] => 19654672
[patent_doc_number] => 12176473
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-12-24
[patent_title] => LED packaging structure
[patent_app_type] => utility
[patent_app_number] => 18/632494
[patent_app_country] => US
[patent_app_date] => 2024-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4193
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632494
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/632494 | LED packaging structure | Apr 10, 2024 | Issued |
Array
(
[id] => 19384706
[patent_doc_number] => 20240274576
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => DIRECT BONDING IN MICROELECTRONIC ASSEMBLIES
[patent_app_type] => utility
[patent_app_number] => 18/632919
[patent_app_country] => US
[patent_app_date] => 2024-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18402
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 32
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632919
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/632919 | Direct bonding in microelectronic assemblies | Apr 10, 2024 | Issued |
Array
(
[id] => 19654463
[patent_doc_number] => 12176263
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-24
[patent_title] => Integrated cooling assembly including coolant channel on the backside semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/620753
[patent_app_country] => US
[patent_app_date] => 2024-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10932
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620753
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/620753 | Integrated cooling assembly including coolant channel on the backside semiconductor device | Mar 27, 2024 | Issued |
Array
(
[id] => 19926281
[patent_doc_number] => 12300574
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-13
[patent_title] => Adhesive and thermal interface material on a plurality of dies covered by a lid
[patent_app_type] => utility
[patent_app_number] => 18/432061
[patent_app_country] => US
[patent_app_date] => 2024-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 2233
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432061
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/432061 | Adhesive and thermal interface material on a plurality of dies covered by a lid | Feb 4, 2024 | Issued |
Array
(
[id] => 19957354
[patent_doc_number] => 12327773
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-10
[patent_title] => Package with underfill containment barrier
[patent_app_type] => utility
[patent_app_number] => 18/415268
[patent_app_country] => US
[patent_app_date] => 2024-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415268
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/415268 | Package with underfill containment barrier | Jan 16, 2024 | Issued |
Array
(
[id] => 19221754
[patent_doc_number] => 20240186458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => HIGH-DENSITY MICRO-LED ARRAYS WITH REFLECTIVE SIDEWALLS
[patent_app_type] => utility
[patent_app_number] => 18/413013
[patent_app_country] => US
[patent_app_date] => 2024-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7964
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413013
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/413013 | HIGH-DENSITY MICRO-LED ARRAYS WITH REFLECTIVE SIDEWALLS | Jan 14, 2024 | Pending |
Array
(
[id] => 19721980
[patent_doc_number] => 12207539
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2025-01-21
[patent_title] => Foldable substrates having a cavity filled with a polymer and methods of making
[patent_app_type] => utility
[patent_app_number] => 18/409627
[patent_app_country] => US
[patent_app_date] => 2024-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 34
[patent_no_of_words] => 52978
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 292
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409627
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/409627 | Foldable substrates having a cavity filled with a polymer and methods of making | Jan 9, 2024 | Issued |