Search

Alonzo Chambliss

Examiner (ID: 15572)

Most Active Art Unit
2897
Art Unit(s)
2897, 2827, 2814, 2892
Total Applications
2378
Issued Applications
2104
Pending Applications
102
Abandoned Applications
209

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17638117 [patent_doc_number] => 11348851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Case with a plurality of pair case components for a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/106636 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4300 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106636 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106636
Case with a plurality of pair case components for a semiconductor device Nov 29, 2020 Issued
Array ( [id] => 17630668 [patent_doc_number] => 20220165683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => ASSEMBLY STRUCTURE AND METHODS FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/105277 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17105277 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/105277
Method for manufacturing assembly structure by using frame structure on substrate Nov 24, 2020 Issued
Array ( [id] => 17787989 [patent_doc_number] => 11411127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Multi-dimensional integrated circuits having semiconductors mounted on multi-dimensional planes and multi-dimensional memory structure [patent_app_type] => utility [patent_app_number] => 17/102928 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 7376 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102928 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102928
Multi-dimensional integrated circuits having semiconductors mounted on multi-dimensional planes and multi-dimensional memory structure Nov 23, 2020 Issued
Array ( [id] => 16858462 [patent_doc_number] => 20210159207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => METHOD FOR BONDING SEMICONDUCTOR COMPONENTS [patent_app_type] => utility [patent_app_number] => 17/102249 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102249 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102249
Method of direct bonding semiconductor components Nov 22, 2020 Issued
Array ( [id] => 17772409 [patent_doc_number] => 11404361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Method for fabricating package structure having encapsulate sensing chip [patent_app_type] => utility [patent_app_number] => 17/096359 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2640 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096359
Method for fabricating package structure having encapsulate sensing chip Nov 11, 2020 Issued
Array ( [id] => 19029933 [patent_doc_number] => 11929297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Conductive thermal management architecture for electronic devices [patent_app_type] => utility [patent_app_number] => 17/092542 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3943 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17092542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/092542
Conductive thermal management architecture for electronic devices Nov 8, 2020 Issued
Array ( [id] => 17582957 [patent_doc_number] => 20220139812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/088449 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17088449 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/088449
Semiconductor package structure including an encapsulant having a cavity exposing an interposer Nov 2, 2020 Issued
Array ( [id] => 17410265 [patent_doc_number] => 11251163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Semiconductor device having circuit board interposed between two conductor layers [patent_app_type] => utility [patent_app_number] => 17/084413 [patent_app_country] => US [patent_app_date] => 2020-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 35 [patent_no_of_words] => 18615 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/084413
Semiconductor device having circuit board interposed between two conductor layers Oct 28, 2020 Issued
Array ( [id] => 19245670 [patent_doc_number] => 12016133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Circuit board with a conductive bump mounted on an adhesive layer [patent_app_type] => utility [patent_app_number] => 17/083271 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 3767 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17083271 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/083271
Circuit board with a conductive bump mounted on an adhesive layer Oct 27, 2020 Issued
Array ( [id] => 17544393 [patent_doc_number] => 11309529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Photolithographic patterning of organic electronic devices [patent_app_type] => utility [patent_app_number] => 17/082655 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 45 [patent_no_of_words] => 18793 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082655 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/082655
Photolithographic patterning of organic electronic devices Oct 27, 2020 Issued
Array ( [id] => 17536696 [patent_doc_number] => 20220115305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => POWER ELECTRONICS ASSEMBLY HAVING FLIPPED CHIP TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/068070 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068070 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068070
Power electronics assembly having flipped chip transistors Oct 11, 2020 Issued
Array ( [id] => 17700207 [patent_doc_number] => 11373941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Sense MOSFET electrically connected to a source pad via a plurality of source extraction ports [patent_app_type] => utility [patent_app_number] => 17/068446 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5877 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068446 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068446
Sense MOSFET electrically connected to a source pad via a plurality of source extraction ports Oct 11, 2020 Issued
Array ( [id] => 16601591 [patent_doc_number] => 20210028122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => EMI Shielding for Flip Chip Package with Exposed Die Backside [patent_app_type] => utility [patent_app_number] => 17/068482 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068482 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068482
EMI shielding for flip chip package with exposed die backside Oct 11, 2020 Issued
Array ( [id] => 17862849 [patent_doc_number] => 11444010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/060545 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 32 [patent_no_of_words] => 18341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17060545 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/060545
Semiconductor device Sep 30, 2020 Issued
Array ( [id] => 16656667 [patent_doc_number] => 20210053303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => EMBEDDING ELECTRONICS IN HOUSING USING ADDITIVE MANUFACTURING [patent_app_type] => utility [patent_app_number] => 17/039254 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039254 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/039254
Embedding electronics in housing using additive manufacturing Sep 29, 2020 Issued
Array ( [id] => 17509138 [patent_doc_number] => 20220102241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => POWER ELECTRONIC MODULES INCLUDING ONE OR MORE LAYERS INCLUDING A POLYMER PRODUCED VIA A FRONTAL RING-OPENING POLYMERIZATION PROCESS [patent_app_type] => utility [patent_app_number] => 17/036096 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036096 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036096
Power electronic modules including one or more layers including a polymer produced via a frontal ring-opening polymerization process Sep 28, 2020 Issued
Array ( [id] => 18431649 [patent_doc_number] => 11676879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Semiconductor package having a chip carrier and a metal plate sized independently of the chip carrier [patent_app_type] => utility [patent_app_number] => 17/034109 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 7747 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/034109
Semiconductor package having a chip carrier and a metal plate sized independently of the chip carrier Sep 27, 2020 Issued
Array ( [id] => 17500686 [patent_doc_number] => 11289396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Sensing component encapsulated by an encapsulation layer with a roughness surface having a hollow region [patent_app_type] => utility [patent_app_number] => 17/031915 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 11056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031915 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031915
Sensing component encapsulated by an encapsulation layer with a roughness surface having a hollow region Sep 24, 2020 Issued
Array ( [id] => 17623205 [patent_doc_number] => 11342269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Package structure with reinforcement structures in a redistribution circuit structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/031906 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 9822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031906
Package structure with reinforcement structures in a redistribution circuit structure and manufacturing method thereof Sep 24, 2020 Issued
Array ( [id] => 19314421 [patent_doc_number] => 12040246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Chip-scale package architectures containing a die back side metal and a solder thermal interface material [patent_app_type] => utility [patent_app_number] => 17/033080 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 9036 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033080
Chip-scale package architectures containing a die back side metal and a solder thermal interface material Sep 24, 2020 Issued
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