Search

Alonzo Chambliss

Examiner (ID: 7113, Phone: (571)272-1927 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2814, 2827, 2892, 2897
Total Applications
2434
Issued Applications
2138
Pending Applications
110
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19721959 [patent_doc_number] => 12207518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Display substrate with pixel defining layers having communication slots in gaps between adjacent rows of sub-pixels [patent_app_type] => utility [patent_app_number] => 17/762318 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 6917 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17762318 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/762318
Display substrate with pixel defining layers having communication slots in gaps between adjacent rows of sub-pixels May 20, 2021 Issued
Array ( [id] => 18024333 [patent_doc_number] => 20220375832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => Method of Forming a Semiconductor Package with Connection Lug [patent_app_type] => utility [patent_app_number] => 17/325727 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17325727 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/325727
Method of forming a semiconductor package with connection lug May 19, 2021 Issued
Array ( [id] => 17262802 [patent_doc_number] => 20210375787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => LEAD FRAME SURFACE FINISHING [patent_app_type] => utility [patent_app_number] => 17/322712 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322712 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322712
Lead frame surface finishing May 16, 2021 Issued
Array ( [id] => 17070920 [patent_doc_number] => 20210273137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => LIGHT-EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 17/321078 [patent_app_country] => US [patent_app_date] => 2021-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321078 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/321078
Light-emitting device with a plurality of electrodes on a semiconductor stack May 13, 2021 Issued
Array ( [id] => 17780149 [patent_doc_number] => 20220246499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => LEAD FRAMES FOR SEMICONDUCTOR PACKAGES WITH INCREASED RELIABILITY AND RELATED SEMICONDUCTOR DEVICE PACKAGES AND METHODS [patent_app_type] => utility [patent_app_number] => 17/314535 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17314535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/314535
Lead frames for semiconductor packages with increased reliability and related semiconductor device packages and methods May 6, 2021 Issued
Array ( [id] => 18387331 [patent_doc_number] => 11658124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Connection structure embedded substrate [patent_app_type] => utility [patent_app_number] => 17/313310 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7612 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313310 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/313310
Connection structure embedded substrate May 5, 2021 Issued
Array ( [id] => 17956362 [patent_doc_number] => 11482475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Ground wing portion for electronic package device [patent_app_type] => utility [patent_app_number] => 17/306955 [patent_app_country] => US [patent_app_date] => 2021-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6512 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306955
Ground wing portion for electronic package device May 3, 2021 Issued
Array ( [id] => 18431654 [patent_doc_number] => 11676884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Cantilevered leadframe support structure for magnetic wireless transfer between integrated circuit dies [patent_app_type] => utility [patent_app_number] => 17/242121 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242121
Cantilevered leadframe support structure for magnetic wireless transfer between integrated circuit dies Apr 26, 2021 Issued
Array ( [id] => 18016464 [patent_doc_number] => 11508771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Image sensors [patent_app_type] => utility [patent_app_number] => 17/240120 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12406 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240120 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/240120
Image sensors Apr 25, 2021 Issued
Array ( [id] => 19767461 [patent_doc_number] => 12225777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Pixel regions having curved surfaces between first and second definition layers [patent_app_type] => utility [patent_app_number] => 17/629026 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6514 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17629026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/629026
Pixel regions having curved surfaces between first and second definition layers Apr 22, 2021 Issued
Array ( [id] => 17188810 [patent_doc_number] => 20210335695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => WIRING SUBSTRATE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/233786 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233786 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/233786
Wiring structure having stacked first and second electrodes Apr 18, 2021 Issued
Array ( [id] => 18190634 [patent_doc_number] => 11581235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => IC package including multi-chip unit with bonded integrated heat spreader [patent_app_type] => utility [patent_app_number] => 17/234671 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234671 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/234671
IC package including multi-chip unit with bonded integrated heat spreader Apr 18, 2021 Issued
Array ( [id] => 18032211 [patent_doc_number] => 11515411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Silicon rich nitride layer between a plurality of semiconductor layers [patent_app_type] => utility [patent_app_number] => 17/232201 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 9340 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 435 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232201
Silicon rich nitride layer between a plurality of semiconductor layers Apr 15, 2021 Issued
Array ( [id] => 17941782 [patent_doc_number] => 11476242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Cascode power electronic device packaging method and packaging structure thereof [patent_app_type] => utility [patent_app_number] => 17/229880 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 49 [patent_no_of_words] => 6006 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229880 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/229880
Cascode power electronic device packaging method and packaging structure thereof Apr 13, 2021 Issued
Array ( [id] => 18766964 [patent_doc_number] => 11817374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Electronic device with exposed tie bar [patent_app_type] => utility [patent_app_number] => 17/229955 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 4110 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/229955
Electronic device with exposed tie bar Apr 13, 2021 Issued
Array ( [id] => 18520814 [patent_doc_number] => 11710709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Terminal member made of plurality of metal layers between two heat sinks [patent_app_type] => utility [patent_app_number] => 17/228033 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 12831 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17228033 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/228033
Terminal member made of plurality of metal layers between two heat sinks Apr 11, 2021 Issued
Array ( [id] => 17174121 [patent_doc_number] => 20210327792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => PACKAGED STACKABLE ELECTRONIC POWER DEVICE FOR SURFACE MOUNTING AND CIRCUIT ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 17/227030 [patent_app_country] => US [patent_app_date] => 2021-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227030 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/227030
Packaged stackable electronic power device for surface mounting and circuit arrangement Apr 8, 2021 Issued
Array ( [id] => 17485990 [patent_doc_number] => 20220093494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => LEAD FRAME [patent_app_type] => utility [patent_app_number] => 17/225683 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225683
Lead frame having a die pad with a plurality of grooves on an underside Apr 7, 2021 Issued
Array ( [id] => 17917570 [patent_doc_number] => 20220319966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => ISOLATED TEMPERATURE SENSOR DEVICE PACKAGE [patent_app_type] => utility [patent_app_number] => 17/219830 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219830
Isolated temperature sensor device package Mar 30, 2021 Issued
Array ( [id] => 16966203 [patent_doc_number] => 20210217702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => SYSTEMS AND METHODS FOR INTERCONNECTING DIES [patent_app_type] => utility [patent_app_number] => 17/216278 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216278 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216278
Die-to-die routing through a seal ring Mar 28, 2021 Issued
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