
Alonzo Chambliss
Examiner (ID: 3784, Phone: (571)272-1927 , Office: P/2897 )
| Most Active Art Unit | 2897 |
| Art Unit(s) | 2897, 2814, 2827, 2892 |
| Total Applications | 2405 |
| Issued Applications | 2120 |
| Pending Applications | 104 |
| Abandoned Applications | 210 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17862849
[patent_doc_number] => 11444010
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-13
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/060545
[patent_app_country] => US
[patent_app_date] => 2020-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 32
[patent_no_of_words] => 18341
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17060545
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/060545 | Semiconductor device | Sep 30, 2020 | Issued |
Array
(
[id] => 16656667
[patent_doc_number] => 20210053303
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-25
[patent_title] => EMBEDDING ELECTRONICS IN HOUSING USING ADDITIVE MANUFACTURING
[patent_app_type] => utility
[patent_app_number] => 17/039254
[patent_app_country] => US
[patent_app_date] => 2020-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4573
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039254
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/039254 | Embedding electronics in housing using additive manufacturing | Sep 29, 2020 | Issued |
Array
(
[id] => 17509138
[patent_doc_number] => 20220102241
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-31
[patent_title] => POWER ELECTRONIC MODULES INCLUDING ONE OR MORE LAYERS INCLUDING A POLYMER PRODUCED VIA A FRONTAL RING-OPENING POLYMERIZATION PROCESS
[patent_app_type] => utility
[patent_app_number] => 17/036096
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4808
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036096
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/036096 | Power electronic modules including one or more layers including a polymer produced via a frontal ring-opening polymerization process | Sep 28, 2020 | Issued |
Array
(
[id] => 18431649
[patent_doc_number] => 11676879
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Semiconductor package having a chip carrier and a metal plate sized independently of the chip carrier
[patent_app_type] => utility
[patent_app_number] => 17/034109
[patent_app_country] => US
[patent_app_date] => 2020-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 7747
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034109
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/034109 | Semiconductor package having a chip carrier and a metal plate sized independently of the chip carrier | Sep 27, 2020 | Issued |
Array
(
[id] => 17623205
[patent_doc_number] => 11342269
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-24
[patent_title] => Package structure with reinforcement structures in a redistribution circuit structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/031906
[patent_app_country] => US
[patent_app_date] => 2020-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 21
[patent_no_of_words] => 9822
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031906
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/031906 | Package structure with reinforcement structures in a redistribution circuit structure and manufacturing method thereof | Sep 24, 2020 | Issued |
Array
(
[id] => 19314421
[patent_doc_number] => 12040246
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-16
[patent_title] => Chip-scale package architectures containing a die back side metal and a solder thermal interface material
[patent_app_type] => utility
[patent_app_number] => 17/033080
[patent_app_country] => US
[patent_app_date] => 2020-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 19
[patent_no_of_words] => 9036
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033080
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/033080 | Chip-scale package architectures containing a die back side metal and a solder thermal interface material | Sep 24, 2020 | Issued |
Array
(
[id] => 17500686
[patent_doc_number] => 11289396
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-29
[patent_title] => Sensing component encapsulated by an encapsulation layer with a roughness surface having a hollow region
[patent_app_type] => utility
[patent_app_number] => 17/031915
[patent_app_country] => US
[patent_app_date] => 2020-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 28
[patent_no_of_words] => 11056
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031915
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/031915 | Sensing component encapsulated by an encapsulation layer with a roughness surface having a hollow region | Sep 24, 2020 | Issued |
Array
(
[id] => 17339423
[patent_doc_number] => 20220005754
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-06
[patent_title] => LEAD FRAME PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/031486
[patent_app_country] => US
[patent_app_date] => 2020-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5151
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031486
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/031486 | Lead frame package | Sep 23, 2020 | Issued |
Array
(
[id] => 17188868
[patent_doc_number] => 20210335753
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-28
[patent_title] => Semiconductor Device and Method
[patent_app_type] => utility
[patent_app_number] => 17/028629
[patent_app_country] => US
[patent_app_date] => 2020-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8817
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028629
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/028629 | Chip bonded to a redistribution structure with curved conductive lines | Sep 21, 2020 | Issued |
Array
(
[id] => 17484001
[patent_doc_number] => 20220091505
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-24
[patent_title] => Semiconductor Device and Method of Manufacture
[patent_app_type] => utility
[patent_app_number] => 17/026667
[patent_app_country] => US
[patent_app_date] => 2020-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13732
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026667
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/026667 | Polymer layer in semiconductor device and method of manufacture | Sep 20, 2020 | Issued |
Array
(
[id] => 17486057
[patent_doc_number] => 20220093561
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-24
[patent_title] => DIRECT BONDING IN MICROELECTRONIC ASSEMBLIES
[patent_app_type] => utility
[patent_app_number] => 17/025709
[patent_app_country] => US
[patent_app_date] => 2020-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18356
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025709
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/025709 | Direct bonding in microelectronic assemblies | Sep 17, 2020 | Issued |
Array
(
[id] => 16560413
[patent_doc_number] => 20210005562
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-07
[patent_title] => PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/025831
[patent_app_country] => US
[patent_app_date] => 2020-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12039
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025831
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/025831 | Semiconductor device encapsulated by molding material attached to redestribution layer | Sep 17, 2020 | Issued |
Array
(
[id] => 17224678
[patent_doc_number] => 11177188
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-11-16
[patent_title] => Heat dissipation substrate for multi-chip package
[patent_app_type] => utility
[patent_app_number] => 17/019333
[patent_app_country] => US
[patent_app_date] => 2020-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3913
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019333
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/019333 | Heat dissipation substrate for multi-chip package | Sep 12, 2020 | Issued |
Array
(
[id] => 20452897
[patent_doc_number] => 12515947
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-06
[patent_title] => Method and arrangement for assembly of microchips into a separate substrate
[patent_app_type] => utility
[patent_app_number] => 17/641559
[patent_app_country] => US
[patent_app_date] => 2020-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 32
[patent_no_of_words] => 5765
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17641559
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/641559 | Method and arrangement for assembly of microchips into a separate substrate | Sep 9, 2020 | Issued |
Array
(
[id] => 17638128
[patent_doc_number] => 11348862
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-31
[patent_title] => Source electrode and connector lead with notched portions for a semiconductor package
[patent_app_type] => utility
[patent_app_number] => 17/013351
[patent_app_country] => US
[patent_app_date] => 2020-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3328
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17013351
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/013351 | Source electrode and connector lead with notched portions for a semiconductor package | Sep 3, 2020 | Issued |
Array
(
[id] => 17310183
[patent_doc_number] => 11211310
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-12-28
[patent_title] => Package structures
[patent_app_type] => utility
[patent_app_number] => 17/011251
[patent_app_country] => US
[patent_app_date] => 2020-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3663
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011251
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/011251 | Package structures | Sep 2, 2020 | Issued |
Array
(
[id] => 17623214
[patent_doc_number] => 11342278
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-24
[patent_title] => EMI shielding for flip chip package with exposed die backside
[patent_app_type] => utility
[patent_app_number] => 17/008997
[patent_app_country] => US
[patent_app_date] => 2020-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 26
[patent_no_of_words] => 4461
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008997
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/008997 | EMI shielding for flip chip package with exposed die backside | Aug 31, 2020 | Issued |
Array
(
[id] => 16528735
[patent_doc_number] => 20200402816
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-24
[patent_title] => Release Film as Isolation Film in Package
[patent_app_type] => utility
[patent_app_number] => 17/007679
[patent_app_country] => US
[patent_app_date] => 2020-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8255
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007679
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/007679 | Underfill between a first package and a second package | Aug 30, 2020 | Issued |
Array
(
[id] => 17559175
[patent_doc_number] => 11315897
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-26
[patent_title] => Substrate having an insulating layer with varying height and angle
[patent_app_type] => utility
[patent_app_number] => 17/002143
[patent_app_country] => US
[patent_app_date] => 2020-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 6874
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002143
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/002143 | Substrate having an insulating layer with varying height and angle | Aug 24, 2020 | Issued |
Array
(
[id] => 17855266
[patent_doc_number] => 20220285309
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-08
[patent_title] => VARIABLE STIFFNESS MODULES
[patent_app_type] => utility
[patent_app_number] => 17/637913
[patent_app_country] => US
[patent_app_date] => 2020-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9995
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17637913
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/637913 | Variable stiffness modules | Aug 23, 2020 | Issued |