Search

Alonzo Chambliss

Examiner (ID: 3784, Phone: (571)272-1927 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2814, 2827, 2892
Total Applications
2405
Issued Applications
2120
Pending Applications
104
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16487752 [patent_doc_number] => 20200381361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => CHIP AND PACKAGING METHOD [patent_app_type] => utility [patent_app_number] => 16/997003 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997003 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997003
Encapsulation of a substrate electrically connected to a plurality of pin arrays Aug 18, 2020 Issued
Array ( [id] => 17500687 [patent_doc_number] => 11289397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Heat sink board for a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/995825 [patent_app_country] => US [patent_app_date] => 2020-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3457 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16995825 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/995825
Heat sink board for a semiconductor device Aug 17, 2020 Issued
Array ( [id] => 18704652 [patent_doc_number] => 11791169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Dual step laser processing of an encapsulant of a semiconductor chip package [patent_app_type] => utility [patent_app_number] => 16/993867 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 35 [patent_no_of_words] => 7469 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16993867 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/993867
Dual step laser processing of an encapsulant of a semiconductor chip package Aug 13, 2020 Issued
Array ( [id] => 16660738 [patent_doc_number] => 20210057375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => Power Semiconductor Package and Method for Fabricating a Power Semiconductor Package [patent_app_type] => utility [patent_app_number] => 16/991123 [patent_app_country] => US [patent_app_date] => 2020-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16991123 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/991123
Power semiconductor package and method for fabricating a power semiconductor package Aug 11, 2020 Issued
Array ( [id] => 18680011 [patent_doc_number] => 20230317669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => DISPLAY DEVICE USING SEMICONDUCTOR LIGHT-EMITTING ELEMENT, AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/020516 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18020516 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/020516
DISPLAY DEVICE USING SEMICONDUCTOR LIGHT-EMITTING ELEMENT, AND METHOD FOR MANUFACTURING SAME Aug 10, 2020 Pending
Array ( [id] => 20146787 [patent_doc_number] => 12381134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Semiconductor device with arrangement for terminals connected to multiple switches [patent_app_type] => utility [patent_app_number] => 17/633680 [patent_app_country] => US [patent_app_date] => 2020-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 12430 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17633680 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/633680
Semiconductor device with arrangement for terminals connected to multiple switches Aug 5, 2020 Issued
Array ( [id] => 17439126 [patent_doc_number] => 11264467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Semiconductor device having multi-layer diffusion barrier and method of making the same [patent_app_type] => utility [patent_app_number] => 16/985276 [patent_app_country] => US [patent_app_date] => 2020-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16985276 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/985276
Semiconductor device having multi-layer diffusion barrier and method of making the same Aug 4, 2020 Issued
Array ( [id] => 17700204 [patent_doc_number] => 11373938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Substrate having a plurality of slit portions between semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/943976 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8698 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943976 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/943976
Substrate having a plurality of slit portions between semiconductor devices Jul 29, 2020 Issued
Array ( [id] => 17493461 [patent_doc_number] => 11282775 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-22 [patent_title] => Chip package assembly with stress decoupled interconnect layer [patent_app_type] => utility [patent_app_number] => 16/942930 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5253 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942930 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/942930
Chip package assembly with stress decoupled interconnect layer Jul 29, 2020 Issued
Array ( [id] => 16617238 [patent_doc_number] => 20210035891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/942715 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942715 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/942715
Stacked dies electrically connected to a package substrate by lead terminals Jul 28, 2020 Issued
Array ( [id] => 17381104 [patent_doc_number] => 11239136 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-01 [patent_title] => Adhesive and thermal interface material on a plurality of dies covered by a lid [patent_app_type] => utility [patent_app_number] => 16/941509 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941509 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941509
Adhesive and thermal interface material on a plurality of dies covered by a lid Jul 27, 2020 Issued
Array ( [id] => 17825766 [patent_doc_number] => 11430720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Recess lead for a surface mount package [patent_app_type] => utility [patent_app_number] => 16/940243 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4569 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940243 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/940243
Recess lead for a surface mount package Jul 26, 2020 Issued
Array ( [id] => 16586153 [patent_doc_number] => 20210020555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => METHOD OF MANUFACTURING A THIN SEMICONDUCTOR CHIP USING A DUMMY SIDEWALL LAYER AND A DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 16/927776 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927776 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927776
Thin semiconductor chip using a dummy sidewall layer Jul 12, 2020 Issued
Array ( [id] => 17745878 [patent_doc_number] => 11393964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Plurality of contact electrode connected to a light emitting element [patent_app_type] => utility [patent_app_number] => 16/927758 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 16926 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927758
Plurality of contact electrode connected to a light emitting element Jul 12, 2020 Issued
Array ( [id] => 16858407 [patent_doc_number] => 20210159152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => POWER MODULE AND SUBSTRATE STRUCTURE APPLIED TO POWER MODULES [patent_app_type] => utility [patent_app_number] => 16/924334 [patent_app_country] => US [patent_app_date] => 2020-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6841 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16924334 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/924334
Power module and substrate structure applied to power modules Jul 8, 2020 Issued
Array ( [id] => 19059117 [patent_doc_number] => 11938314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Method of manufacturing an implantable neural electrode interface platform [patent_app_type] => utility [patent_app_number] => 16/921486 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 5375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921486 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921486
Method of manufacturing an implantable neural electrode interface platform Jul 5, 2020 Issued
Array ( [id] => 16660676 [patent_doc_number] => 20210057313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => SEMICONDUCTOR PACKAGE HAVING EXPOSED HEAT SINK FOR HIGH THERMAL CONDUCTIVITY [patent_app_type] => utility [patent_app_number] => 16/912724 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912724 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/912724
Semiconductor package having exposed heat sink for high thermal conductivity Jun 25, 2020 Issued
Array ( [id] => 19552865 [patent_doc_number] => 12136577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Integrated circuit die packages including a contiguous heat spreader [patent_app_type] => utility [patent_app_number] => 16/911820 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 9379 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16911820 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/911820
Integrated circuit die packages including a contiguous heat spreader Jun 24, 2020 Issued
Array ( [id] => 16545002 [patent_doc_number] => 20200411417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => SEMICONDUCTOR PACKAGE WITH A CAVITY IN A DIE PAD FOR REDUCING VOIDS IN THE SOLDER [patent_app_type] => utility [patent_app_number] => 16/910824 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16910824 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/910824
Semiconductor package with a cavity in a die pad for reducing voids in the solder Jun 23, 2020 Issued
Array ( [id] => 17516873 [patent_doc_number] => 11296034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Substrate and semiconductor package comprising an interposer element with a slot and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/905912 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 6693 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905912 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/905912
Substrate and semiconductor package comprising an interposer element with a slot and method of manufacturing the same Jun 17, 2020 Issued
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