Search

Alpesh Shah

Examiner (ID: 10017)

Most Active Art Unit
2302
Art Unit(s)
2302, 2756, 2783, 2315
Total Applications
455
Issued Applications
326
Pending Applications
23
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3465585 [patent_doc_number] => 05379421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Interactive terminal for the access of remote database information' [patent_app_type] => 1 [patent_app_number] => 8/239359 [patent_app_country] => US [patent_app_date] => 1994-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5949 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/379/05379421.pdf [firstpage_image] =>[orig_patent_app_number] => 239359 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/239359
Interactive terminal for the access of remote database information May 5, 1994 Issued
Array ( [id] => 3708381 [patent_doc_number] => 05619660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Keying notches for side contacts on a thin form factor computer card' [patent_app_type] => 1 [patent_app_number] => 8/234481 [patent_app_country] => US [patent_app_date] => 1994-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6510 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619660.pdf [firstpage_image] =>[orig_patent_app_number] => 234481 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/234481
Keying notches for side contacts on a thin form factor computer card Apr 27, 1994 Issued
08/231528 INTELLIGENT MEMORY SYSTEM FOR PROCESSING VARIABLE LENGTH I/O INSTRUCTIONS Apr 21, 1994 Abandoned
08/231203 PCMICIA CARD-LIKE DEVICE WITH INTERNAL RETRACTABLE CORD MECHANISM Apr 20, 1994 Abandoned
Array ( [id] => 3564380 [patent_doc_number] => 05572701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Bus snoop method and apparatus for computer system having CPU with cache and main memory unit' [patent_app_type] => 1 [patent_app_number] => 8/229755 [patent_app_country] => US [patent_app_date] => 1994-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3182 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572701.pdf [firstpage_image] =>[orig_patent_app_number] => 229755 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/229755
Bus snoop method and apparatus for computer system having CPU with cache and main memory unit Apr 18, 1994 Issued
Array ( [id] => 3638678 [patent_doc_number] => 05608909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'Method and system for caching presentation data of a source object in a presentation cache' [patent_app_type] => 1 [patent_app_number] => 8/227970 [patent_app_country] => US [patent_app_date] => 1994-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16963 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/608/05608909.pdf [firstpage_image] =>[orig_patent_app_number] => 227970 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/227970
Method and system for caching presentation data of a source object in a presentation cache Apr 14, 1994 Issued
Array ( [id] => 3603621 [patent_doc_number] => 05586289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Method and apparatus for accessing local storage within a parallel processing computer' [patent_app_type] => 1 [patent_app_number] => 8/228465 [patent_app_country] => US [patent_app_date] => 1994-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6786 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586289.pdf [firstpage_image] =>[orig_patent_app_number] => 228465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/228465
Method and apparatus for accessing local storage within a parallel processing computer Apr 14, 1994 Issued
Array ( [id] => 3556395 [patent_doc_number] => 05555398 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Write back cache coherency module for systems with a write through cache supporting bus' [patent_app_type] => 1 [patent_app_number] => 8/228145 [patent_app_country] => US [patent_app_date] => 1994-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7378 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 380 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555398.pdf [firstpage_image] =>[orig_patent_app_number] => 228145 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/228145
Write back cache coherency module for systems with a write through cache supporting bus Apr 14, 1994 Issued
Array ( [id] => 3427013 [patent_doc_number] => 05454090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Apparatus for furnishing instructions in a microprocessor with a multi-stage pipeline processing unit for processing instruction phase and having a memory and at least three additional memory units' [patent_app_type] => 1 [patent_app_number] => 8/224080 [patent_app_country] => US [patent_app_date] => 1994-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 4357 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/454/05454090.pdf [firstpage_image] =>[orig_patent_app_number] => 224080 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/224080
Apparatus for furnishing instructions in a microprocessor with a multi-stage pipeline processing unit for processing instruction phase and having a memory and at least three additional memory units Apr 6, 1994 Issued
Array ( [id] => 3604532 [patent_doc_number] => 05568627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Header verification in a disk drive using sector histories for improved format efficiency' [patent_app_type] => 1 [patent_app_number] => 8/223415 [patent_app_country] => US [patent_app_date] => 1994-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4838 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568627.pdf [firstpage_image] =>[orig_patent_app_number] => 223415 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/223415
Header verification in a disk drive using sector histories for improved format efficiency Apr 4, 1994 Issued
Array ( [id] => 3458688 [patent_doc_number] => 05421026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Data processor for processing instruction after conditional branch instruction at high speed' [patent_app_type] => 1 [patent_app_number] => 8/220936 [patent_app_country] => US [patent_app_date] => 1994-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4044 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/421/05421026.pdf [firstpage_image] =>[orig_patent_app_number] => 220936 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/220936
Data processor for processing instruction after conditional branch instruction at high speed Mar 30, 1994 Issued
Array ( [id] => 3472373 [patent_doc_number] => 05442789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'System and method for efficiently loading and removing selected functions on digital signal processors without interrupting execution of other functions on the digital signal processors' [patent_app_type] => 1 [patent_app_number] => 8/220959 [patent_app_country] => US [patent_app_date] => 1994-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 52 [patent_no_of_words] => 19580 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/442/05442789.pdf [firstpage_image] =>[orig_patent_app_number] => 220959 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/220959
System and method for efficiently loading and removing selected functions on digital signal processors without interrupting execution of other functions on the digital signal processors Mar 30, 1994 Issued
Array ( [id] => 3458672 [patent_doc_number] => 05421025 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Cell processing system having first and second processing units capable of outputting first and second processed signals at the same time' [patent_app_type] => 1 [patent_app_number] => 8/220357 [patent_app_country] => US [patent_app_date] => 1994-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10458 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 462 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/421/05421025.pdf [firstpage_image] =>[orig_patent_app_number] => 220357 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/220357
Cell processing system having first and second processing units capable of outputting first and second processed signals at the same time Mar 30, 1994 Issued
Array ( [id] => 3708740 [patent_doc_number] => 05680634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Fixed interconnection network method and apparatus for a modular mixed-resolution, N-dimensional configuration control mechanism' [patent_app_type] => 1 [patent_app_number] => 8/218333 [patent_app_country] => US [patent_app_date] => 1994-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 145 [patent_no_of_words] => 22252 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680634.pdf [firstpage_image] =>[orig_patent_app_number] => 218333 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/218333
Fixed interconnection network method and apparatus for a modular mixed-resolution, N-dimensional configuration control mechanism Mar 27, 1994 Issued
Array ( [id] => 3596459 [patent_doc_number] => 05581774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Data processor decoding and executing a train of instructions of variable length at increased speed' [patent_app_type] => 1 [patent_app_number] => 8/213822 [patent_app_country] => US [patent_app_date] => 1994-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3692 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581774.pdf [firstpage_image] =>[orig_patent_app_number] => 213822 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/213822
Data processor decoding and executing a train of instructions of variable length at increased speed Mar 13, 1994 Issued
08/207031 A DATA PROCESSOR HAVING A COMPUTING ELEMENT MOUNTED ON A MICROCONTROLLER Mar 6, 1994 Abandoned
Array ( [id] => 3564394 [patent_doc_number] => 05572702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency' [patent_app_type] => 1 [patent_app_number] => 8/202790 [patent_app_country] => US [patent_app_date] => 1994-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10398 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572702.pdf [firstpage_image] =>[orig_patent_app_number] => 202790 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/202790
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency Feb 27, 1994 Issued
08/205015 METHOD AND APPARATUS FOR SELF-SNOOPING Feb 27, 1994 Abandoned
Array ( [id] => 3471925 [patent_doc_number] => 05442762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Instructing method and execution system for instructions including plural instruction codes' [patent_app_type] => 1 [patent_app_number] => 8/202668 [patent_app_country] => US [patent_app_date] => 1994-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5918 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/442/05442762.pdf [firstpage_image] =>[orig_patent_app_number] => 202668 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/202668
Instructing method and execution system for instructions including plural instruction codes Feb 24, 1994 Issued
Array ( [id] => 3503423 [patent_doc_number] => 05440757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Data processor having multistage store buffer for processing exceptions' [patent_app_type] => 1 [patent_app_number] => 8/200904 [patent_app_country] => US [patent_app_date] => 1994-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 34 [patent_no_of_words] => 17169 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440757.pdf [firstpage_image] =>[orig_patent_app_number] => 200904 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/200904
Data processor having multistage store buffer for processing exceptions Feb 22, 1994 Issued
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