Search

Alpesh Shah

Examiner (ID: 10017)

Most Active Art Unit
2302
Art Unit(s)
2302, 2756, 2783, 2315
Total Applications
455
Issued Applications
326
Pending Applications
23
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4064684 [patent_doc_number] => 05870566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Port expansion network and method for lan hubs' [patent_app_type] => 1 [patent_app_number] => 8/900043 [patent_app_country] => US [patent_app_date] => 1997-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3831 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870566.pdf [firstpage_image] =>[orig_patent_app_number] => 900043 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/900043
Port expansion network and method for lan hubs Jul 23, 1997 Issued
Array ( [id] => 3849066 [patent_doc_number] => 05761427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method and apparatus for updating host memory in an adapter to minimize host CPU overhead in servicing an interrupt' [patent_app_type] => 1 [patent_app_number] => 8/892331 [patent_app_country] => US [patent_app_date] => 1997-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5682 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761427.pdf [firstpage_image] =>[orig_patent_app_number] => 892331 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892331
Method and apparatus for updating host memory in an adapter to minimize host CPU overhead in servicing an interrupt Jul 13, 1997 Issued
Array ( [id] => 3905351 [patent_doc_number] => 05778242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Software interrupt generator for computer bus interface' [patent_app_type] => 1 [patent_app_number] => 8/893903 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7079 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778242.pdf [firstpage_image] =>[orig_patent_app_number] => 893903 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/893903
Software interrupt generator for computer bus interface Jul 10, 1997 Issued
Array ( [id] => 4057124 [patent_doc_number] => 05875301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Method and apparatus for the addition and removal of nodes from a common interconnect' [patent_app_type] => 1 [patent_app_number] => 8/889814 [patent_app_country] => US [patent_app_date] => 1997-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 8688 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875301.pdf [firstpage_image] =>[orig_patent_app_number] => 889814 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/889814
Method and apparatus for the addition and removal of nodes from a common interconnect Jul 7, 1997 Issued
Array ( [id] => 3888403 [patent_doc_number] => 05838988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Computer product for precise architectural update in an out-of-order processor' [patent_app_type] => 1 [patent_app_number] => 8/882219 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7056 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838988.pdf [firstpage_image] =>[orig_patent_app_number] => 882219 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882219
Computer product for precise architectural update in an out-of-order processor Jun 24, 1997 Issued
Array ( [id] => 3803405 [patent_doc_number] => 05822604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Method of optimizing recognition of collective data movement in a parallel distributed system' [patent_app_type] => 1 [patent_app_number] => 8/873472 [patent_app_country] => US [patent_app_date] => 1997-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6927 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822604.pdf [firstpage_image] =>[orig_patent_app_number] => 873472 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873472
Method of optimizing recognition of collective data movement in a parallel distributed system Jun 11, 1997 Issued
Array ( [id] => 3803466 [patent_doc_number] => 05822607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Method for fast validation checking for code and data segment descriptor loads' [patent_app_type] => 1 [patent_app_number] => 8/871039 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5786 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822607.pdf [firstpage_image] =>[orig_patent_app_number] => 871039 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871039
Method for fast validation checking for code and data segment descriptor loads Jun 8, 1997 Issued
Array ( [id] => 4039949 [patent_doc_number] => 05884027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Architecture for an I/O processor that integrates a PCI to PCI bridge' [patent_app_type] => 1 [patent_app_number] => 8/870141 [patent_app_country] => US [patent_app_date] => 1997-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 27512 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/884/05884027.pdf [firstpage_image] =>[orig_patent_app_number] => 870141 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/870141
Architecture for an I/O processor that integrates a PCI to PCI bridge Jun 4, 1997 Issued
Array ( [id] => 3951551 [patent_doc_number] => 05872932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Persistence specification system and method for producing persistent and transient submaps in a management station for a data communication network' [patent_app_type] => 1 [patent_app_number] => 8/868248 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 9545 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872932.pdf [firstpage_image] =>[orig_patent_app_number] => 868248 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868248
Persistence specification system and method for producing persistent and transient submaps in a management station for a data communication network Jun 2, 1997 Issued
Array ( [id] => 4057731 [patent_doc_number] => 05875339 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Asynchronous arbiter using multiple arbiter elements to enhance speed' [patent_app_type] => 1 [patent_app_number] => 8/857767 [patent_app_country] => US [patent_app_date] => 1997-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875339.pdf [firstpage_image] =>[orig_patent_app_number] => 857767 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857767
Asynchronous arbiter using multiple arbiter elements to enhance speed May 14, 1997 Issued
Array ( [id] => 3745956 [patent_doc_number] => 05694614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Minimum latency bus interface circuit with reduced I/O pin count through multi-mode operation' [patent_app_type] => 1 [patent_app_number] => 8/848985 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6992 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694614.pdf [firstpage_image] =>[orig_patent_app_number] => 848985 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/848985
Minimum latency bus interface circuit with reduced I/O pin count through multi-mode operation Apr 29, 1997 Issued
Array ( [id] => 4018386 [patent_doc_number] => 05860021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Single chip microcontroller having down-loadable memory organization supporting \"shadow\" personality, optimized for bi-directional data transfers over a communication channel' [patent_app_type] => 1 [patent_app_number] => 8/846118 [patent_app_country] => US [patent_app_date] => 1997-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8047 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860021.pdf [firstpage_image] =>[orig_patent_app_number] => 846118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/846118
Single chip microcontroller having down-loadable memory organization supporting "shadow" personality, optimized for bi-directional data transfers over a communication channel Apr 23, 1997 Issued
Array ( [id] => 3895199 [patent_doc_number] => 05799202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Video terminal architecture without dedicated memory' [patent_app_type] => 1 [patent_app_number] => 8/839102 [patent_app_country] => US [patent_app_date] => 1997-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 8304 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/799/05799202.pdf [firstpage_image] =>[orig_patent_app_number] => 839102 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839102
Video terminal architecture without dedicated memory Apr 15, 1997 Issued
Array ( [id] => 3896729 [patent_doc_number] => 05805808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Real time parser for data packets in a communications network' [patent_app_type] => 1 [patent_app_number] => 8/838678 [patent_app_country] => US [patent_app_date] => 1997-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 32 [patent_no_of_words] => 14359 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805808.pdf [firstpage_image] =>[orig_patent_app_number] => 838678 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/838678
Real time parser for data packets in a communications network Apr 8, 1997 Issued
Array ( [id] => 3952429 [patent_doc_number] => 05872988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Parallel data processing device having a concatenated data path between elementary processors' [patent_app_type] => 1 [patent_app_number] => 8/823003 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3755 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872988.pdf [firstpage_image] =>[orig_patent_app_number] => 823003 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/823003
Parallel data processing device having a concatenated data path between elementary processors Mar 20, 1997 Issued
Array ( [id] => 3898734 [patent_doc_number] => 05748950 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Method and apparatus for providing an optimized compare-and-branch instruction' [patent_app_type] => 1 [patent_app_number] => 8/821029 [patent_app_country] => US [patent_app_date] => 1997-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3717 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748950.pdf [firstpage_image] =>[orig_patent_app_number] => 821029 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/821029
Method and apparatus for providing an optimized compare-and-branch instruction Mar 19, 1997 Issued
Array ( [id] => 3797318 [patent_doc_number] => 05758179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Bus operation circuit using CMOS ratio logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/805943 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 3170 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/758/05758179.pdf [firstpage_image] =>[orig_patent_app_number] => 805943 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/805943
Bus operation circuit using CMOS ratio logic circuits Feb 20, 1997 Issued
Array ( [id] => 3700380 [patent_doc_number] => 05696934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Method of utilizing storage disks of differing capacity in a single storage volume in a hierarchial disk array' [patent_app_type] => 1 [patent_app_number] => 8/797214 [patent_app_country] => US [patent_app_date] => 1997-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6046 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696934.pdf [firstpage_image] =>[orig_patent_app_number] => 797214 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/797214
Method of utilizing storage disks of differing capacity in a single storage volume in a hierarchial disk array Feb 10, 1997 Issued
Array ( [id] => 3802466 [patent_doc_number] => 05737528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Network connecting apparatus with separate data and control signal lines' [patent_app_type] => 1 [patent_app_number] => 8/792071 [patent_app_country] => US [patent_app_date] => 1997-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4868 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737528.pdf [firstpage_image] =>[orig_patent_app_number] => 792071 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/792071
Network connecting apparatus with separate data and control signal lines Feb 9, 1997 Issued
Array ( [id] => 3804063 [patent_doc_number] => 05737627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Pipelined data ordering system utilizing state machines to order data requests' [patent_app_type] => 1 [patent_app_number] => 8/796343 [patent_app_country] => US [patent_app_date] => 1997-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6422 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737627.pdf [firstpage_image] =>[orig_patent_app_number] => 796343 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/796343
Pipelined data ordering system utilizing state machines to order data requests Feb 6, 1997 Issued
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