| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3778426
[patent_doc_number] => 05845079
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Mobile migration communication control device'
[patent_app_type] => 1
[patent_app_number] => 8/635027
[patent_app_country] => US
[patent_app_date] => 1996-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 85
[patent_no_of_words] => 25550
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 277
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/845/05845079.pdf
[firstpage_image] =>[orig_patent_app_number] => 635027
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/635027 | Mobile migration communication control device | Apr 18, 1996 | Issued |
Array
(
[id] => 3812305
[patent_doc_number] => 05781791
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Digital microelectronic circuit package using buffer dies and programmable device or memory dies'
[patent_app_type] => 1
[patent_app_number] => 8/636996
[patent_app_country] => US
[patent_app_date] => 1996-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 966
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/781/05781791.pdf
[firstpage_image] =>[orig_patent_app_number] => 636996
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/636996 | Digital microelectronic circuit package using buffer dies and programmable device or memory dies | Apr 15, 1996 | Issued |
Array
(
[id] => 4082111
[patent_doc_number] => 05867726
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'Microcomputer'
[patent_app_type] => 1
[patent_app_number] => 8/630320
[patent_app_country] => US
[patent_app_date] => 1996-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 19209
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/867/05867726.pdf
[firstpage_image] =>[orig_patent_app_number] => 630320
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/630320 | Microcomputer | Apr 9, 1996 | Issued |
Array
(
[id] => 3871585
[patent_doc_number] => 05768509
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Short message server without local customer database'
[patent_app_type] => 1
[patent_app_number] => 8/628902
[patent_app_country] => US
[patent_app_date] => 1996-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2764
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/768/05768509.pdf
[firstpage_image] =>[orig_patent_app_number] => 628902
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/628902 | Short message server without local customer database | Apr 7, 1996 | Issued |
| 08/628467 | ORDERED AND RELIABLE MAINTENANCE OF INTER-PROCESS RELATIONSHIPS IN A DISTRIBUTED MULTIPROCESSOR | Apr 4, 1996 | Abandoned |
Array
(
[id] => 3848400
[patent_doc_number] => 05740418
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'Pipelined processor carrying out branch prediction by BTB'
[patent_app_type] => 1
[patent_app_number] => 8/625180
[patent_app_country] => US
[patent_app_date] => 1996-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7143
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/740/05740418.pdf
[firstpage_image] =>[orig_patent_app_number] => 625180
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/625180 | Pipelined processor carrying out branch prediction by BTB | Mar 28, 1996 | Issued |
Array
(
[id] => 3850467
[patent_doc_number] => 05761521
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Processor for character strings of variable length'
[patent_app_type] => 1
[patent_app_number] => 8/619496
[patent_app_country] => US
[patent_app_date] => 1996-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4537
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 309
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/761/05761521.pdf
[firstpage_image] =>[orig_patent_app_number] => 619496
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/619496 | Processor for character strings of variable length | Mar 25, 1996 | Issued |
Array
(
[id] => 3998693
[patent_doc_number] => 05862400
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-19
[patent_title] => 'Formula processor having cache means for storing and retrieving results of previously computed formulas based on identification and dependency information'
[patent_app_type] => 1
[patent_app_number] => 8/618056
[patent_app_country] => US
[patent_app_date] => 1996-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 20
[patent_no_of_words] => 18105
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/862/05862400.pdf
[firstpage_image] =>[orig_patent_app_number] => 618056
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/618056 | Formula processor having cache means for storing and retrieving results of previously computed formulas based on identification and dependency information | Mar 24, 1996 | Issued |
Array
(
[id] => 3797308
[patent_doc_number] => 05819102
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'Formula processor having cache means for storing and retrieving results of previously computed formulas base on identification and dependency informations'
[patent_app_type] => 1
[patent_app_number] => 8/618013
[patent_app_country] => US
[patent_app_date] => 1996-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 20
[patent_no_of_words] => 18101
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/819/05819102.pdf
[firstpage_image] =>[orig_patent_app_number] => 618013
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/618013 | Formula processor having cache means for storing and retrieving results of previously computed formulas base on identification and dependency informations | Mar 24, 1996 | Issued |
Array
(
[id] => 3633818
[patent_doc_number] => 05689644
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-18
[patent_title] => 'Network switch with arbitration sytem'
[patent_app_type] => 1
[patent_app_number] => 8/621422
[patent_app_country] => US
[patent_app_date] => 1996-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 22
[patent_no_of_words] => 14790
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 259
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/689/05689644.pdf
[firstpage_image] =>[orig_patent_app_number] => 621422
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/621422 | Network switch with arbitration sytem | Mar 24, 1996 | Issued |
Array
(
[id] => 3677119
[patent_doc_number] => 05598574
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Vector processing device'
[patent_app_type] => 1
[patent_app_number] => 8/617148
[patent_app_country] => US
[patent_app_date] => 1996-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 6246
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/598/05598574.pdf
[firstpage_image] =>[orig_patent_app_number] => 617148
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/617148 | Vector processing device | Mar 17, 1996 | Issued |
| 08/605804 | DATA PROCESSOR HAVING A COMPUTING ELEMENT MOUNTED ON A MICROCONTROLLER | Feb 22, 1996 | Abandoned |
Array
(
[id] => 3625607
[patent_doc_number] => 05566316
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Method and apparatus for hierarchical management of data storage elements in an array storage device'
[patent_app_type] => 1
[patent_app_number] => 8/606223
[patent_app_country] => US
[patent_app_date] => 1996-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5642
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 298
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/566/05566316.pdf
[firstpage_image] =>[orig_patent_app_number] => 606223
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/606223 | Method and apparatus for hierarchical management of data storage elements in an array storage device | Feb 22, 1996 | Issued |
Array
(
[id] => 3661212
[patent_doc_number] => 05640588
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-17
[patent_title] => 'CPU architecture performing dynamic instruction scheduling at time of execution within single clock cycle'
[patent_app_type] => 1
[patent_app_number] => 8/592989
[patent_app_country] => US
[patent_app_date] => 1996-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 34
[patent_no_of_words] => 25989
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 403
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/640/05640588.pdf
[firstpage_image] =>[orig_patent_app_number] => 592989
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/592989 | CPU architecture performing dynamic instruction scheduling at time of execution within single clock cycle | Jan 28, 1996 | Issued |
Array
(
[id] => 3637248
[patent_doc_number] => 05603048
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-11
[patent_title] => 'Microprocessor with bus sizing function'
[patent_app_type] => 1
[patent_app_number] => 8/582022
[patent_app_country] => US
[patent_app_date] => 1996-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5588
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/603/05603048.pdf
[firstpage_image] =>[orig_patent_app_number] => 582022
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/582022 | Microprocessor with bus sizing function | Jan 1, 1996 | Issued |
Array
(
[id] => 3696062
[patent_doc_number] => 05634136
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-27
[patent_title] => 'Data processor and method of controlling the same'
[patent_app_type] => 1
[patent_app_number] => 8/569866
[patent_app_country] => US
[patent_app_date] => 1995-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 8805
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 293
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/634/05634136.pdf
[firstpage_image] =>[orig_patent_app_number] => 569866
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/569866 | Data processor and method of controlling the same | Dec 7, 1995 | Issued |
Array
(
[id] => 3639878
[patent_doc_number] => 05621895
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-15
[patent_title] => 'Frame-structured bus system for transmitting both synchronous and asynchronous data over a star-coupled local operation network'
[patent_app_type] => 1
[patent_app_number] => 8/566741
[patent_app_country] => US
[patent_app_date] => 1995-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 7856
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 363
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/621/05621895.pdf
[firstpage_image] =>[orig_patent_app_number] => 566741
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/566741 | Frame-structured bus system for transmitting both synchronous and asynchronous data over a star-coupled local operation network | Dec 3, 1995 | Issued |
Array
(
[id] => 3812951
[patent_doc_number] => 05828846
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Controlling passage of packets or messages via a virtual connection or flow'
[patent_app_type] => 1
[patent_app_number] => 8/561790
[patent_app_country] => US
[patent_app_date] => 1995-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2678
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/828/05828846.pdf
[firstpage_image] =>[orig_patent_app_number] => 561790
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/561790 | Controlling passage of packets or messages via a virtual connection or flow | Nov 21, 1995 | Issued |
Array
(
[id] => 3855201
[patent_doc_number] => 05708839
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-13
[patent_title] => 'Method and apparatus for providing bus protocol simulation'
[patent_app_type] => 1
[patent_app_number] => 8/560940
[patent_app_country] => US
[patent_app_date] => 1995-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 120
[patent_figures_cnt] => 22
[patent_no_of_words] => 7268
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/708/05708839.pdf
[firstpage_image] =>[orig_patent_app_number] => 560940
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/560940 | Method and apparatus for providing bus protocol simulation | Nov 19, 1995 | Issued |
Array
(
[id] => 3622276
[patent_doc_number] => 05590370
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-31
[patent_title] => 'Intelligent memory system for processing varibable length I/O instructions'
[patent_app_type] => 1
[patent_app_number] => 8/558208
[patent_app_country] => US
[patent_app_date] => 1995-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4177
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/590/05590370.pdf
[firstpage_image] =>[orig_patent_app_number] => 558208
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/558208 | Intelligent memory system for processing varibable length I/O instructions | Nov 15, 1995 | Issued |