Search

Alpesh Shah

Examiner (ID: 17956)

Most Active Art Unit
2302
Art Unit(s)
2315, 2302, 2756, 2783
Total Applications
455
Issued Applications
326
Pending Applications
23
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
08/555466 ADAPTER FOR INTERCONNECTING SINGLE-ENDED AND DIFFERENTIAL SCSI BUSES Nov 12, 1995 Abandoned
Array ( [id] => 3830898 [patent_doc_number] => 05812866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Parallel processor with controllable relation between input and output data' [patent_app_type] => 1 [patent_app_number] => 8/546769 [patent_app_country] => US [patent_app_date] => 1995-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 36 [patent_no_of_words] => 5356 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812866.pdf [firstpage_image] =>[orig_patent_app_number] => 546769 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/546769
Parallel processor with controllable relation between input and output data Oct 22, 1995 Issued
Array ( [id] => 3673229 [patent_doc_number] => 05592681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Data processing with improved register bit structure' [patent_app_type] => 1 [patent_app_number] => 8/543349 [patent_app_country] => US [patent_app_date] => 1995-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2660 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592681.pdf [firstpage_image] =>[orig_patent_app_number] => 543349 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/543349
Data processing with improved register bit structure Oct 15, 1995 Issued
Array ( [id] => 4064635 [patent_doc_number] => 05870563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Method and apparatus for optimizing message transmission' [patent_app_type] => 1 [patent_app_number] => 8/540506 [patent_app_country] => US [patent_app_date] => 1995-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4766 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870563.pdf [firstpage_image] =>[orig_patent_app_number] => 540506 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540506
Method and apparatus for optimizing message transmission Oct 10, 1995 Issued
Array ( [id] => 3888388 [patent_doc_number] => 05838987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Processor for eliminating external isochronous subsystems' [patent_app_type] => 1 [patent_app_number] => 8/540351 [patent_app_country] => US [patent_app_date] => 1995-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3971 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838987.pdf [firstpage_image] =>[orig_patent_app_number] => 540351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540351
Processor for eliminating external isochronous subsystems Oct 5, 1995 Issued
Array ( [id] => 3903511 [patent_doc_number] => 05724600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Parallel processor system' [patent_app_type] => 1 [patent_app_number] => 8/525171 [patent_app_country] => US [patent_app_date] => 1995-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 49 [patent_no_of_words] => 30917 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724600.pdf [firstpage_image] =>[orig_patent_app_number] => 525171 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/525171
Parallel processor system Sep 7, 1995 Issued
08/522115 NETWORK INTERCONNECTION APPARATUS, NETWORK NODE APPARATUS, AND PACKET TRANSFER METHOD FOR HIGH SPEED, LARGE CAPACITY INTER-NETWORK COMMUNICATION Aug 30, 1995 Abandoned
Array ( [id] => 3829139 [patent_doc_number] => 05771391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Computer processor having a pipelined architecture and method of using same' [patent_app_type] => 1 [patent_app_number] => 8/520666 [patent_app_country] => US [patent_app_date] => 1995-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 11153 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771391.pdf [firstpage_image] =>[orig_patent_app_number] => 520666 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/520666
Computer processor having a pipelined architecture and method of using same Aug 27, 1995 Issued
Array ( [id] => 3776733 [patent_doc_number] => 05742840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'General purpose, multiple precision parallel operation, programmable media processor' [patent_app_type] => 1 [patent_app_number] => 8/516036 [patent_app_country] => US [patent_app_date] => 1995-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 15401 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742840.pdf [firstpage_image] =>[orig_patent_app_number] => 516036 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/516036
General purpose, multiple precision parallel operation, programmable media processor Aug 15, 1995 Issued
Array ( [id] => 3718200 [patent_doc_number] => 05655080 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Distributed hash group-by cooperative processing' [patent_app_type] => 1 [patent_app_number] => 8/514543 [patent_app_country] => US [patent_app_date] => 1995-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2346 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/655/05655080.pdf [firstpage_image] =>[orig_patent_app_number] => 514543 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/514543
Distributed hash group-by cooperative processing Aug 13, 1995 Issued
Array ( [id] => 3701210 [patent_doc_number] => 05696986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Computer processor utilizing logarithmic conversion and method of use thereof' [patent_app_type] => 1 [patent_app_number] => 8/512849 [patent_app_country] => US [patent_app_date] => 1995-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5610 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696986.pdf [firstpage_image] =>[orig_patent_app_number] => 512849 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/512849
Computer processor utilizing logarithmic conversion and method of use thereof Aug 8, 1995 Issued
Array ( [id] => 3621002 [patent_doc_number] => 05590285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Network station with multiple network addresses' [patent_app_type] => 1 [patent_app_number] => 8/513167 [patent_app_country] => US [patent_app_date] => 1995-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 16087 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590285.pdf [firstpage_image] =>[orig_patent_app_number] => 513167 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/513167
Network station with multiple network addresses Aug 8, 1995 Issued
Array ( [id] => 3717355 [patent_doc_number] => 05675823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Grain structured processing architecture device and a method for processing three dimensional volume element data' [patent_app_type] => 1 [patent_app_number] => 8/512258 [patent_app_country] => US [patent_app_date] => 1995-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 2902 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675823.pdf [firstpage_image] =>[orig_patent_app_number] => 512258 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/512258
Grain structured processing architecture device and a method for processing three dimensional volume element data Aug 6, 1995 Issued
08/506945 METHOD FOR REPROGRAMMING A COMMUNICATION UNIT'S ACCESS TO A WIRELES COMMUNICATION SYSTEM Jul 26, 1995 Abandoned
Array ( [id] => 3637208 [patent_doc_number] => 05603046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Method for complex data movement in a multi-processor data processing system' [patent_app_type] => 1 [patent_app_number] => 8/506257 [patent_app_country] => US [patent_app_date] => 1995-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 120 [patent_figures_cnt] => 122 [patent_no_of_words] => 7513 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/603/05603046.pdf [firstpage_image] =>[orig_patent_app_number] => 506257 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/506257
Method for complex data movement in a multi-processor data processing system Jul 23, 1995 Issued
08/497356 A PIPELINED CUP WITH INSTRUCTION FETCH, EXECUTION AND WRITE BACK STAGES Jun 29, 1995 Abandoned
Array ( [id] => 3567118 [patent_doc_number] => 05574939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Multiprocessor coupling system with integrated compile and run time scheduling for parallelism' [patent_app_type] => 1 [patent_app_number] => 8/496462 [patent_app_country] => US [patent_app_date] => 1995-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7741 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574939.pdf [firstpage_image] =>[orig_patent_app_number] => 496462 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/496462
Multiprocessor coupling system with integrated compile and run time scheduling for parallelism Jun 28, 1995 Issued
Array ( [id] => 3668195 [patent_doc_number] => 05623687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Reset configuration in a data processing system and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/494664 [patent_app_country] => US [patent_app_date] => 1995-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 11567 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623687.pdf [firstpage_image] =>[orig_patent_app_number] => 494664 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/494664
Reset configuration in a data processing system and method therefor Jun 25, 1995 Issued
08/490654 ARCHITECTURE FOR AN I/O PROCESSOR THAT INTEGRATES A PCI TO PCI BRIDGE Jun 14, 1995 Abandoned
Array ( [id] => 3708344 [patent_doc_number] => 05596767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Programmable data processing system and apparatus for executing both general purpose instructions and special purpose graphic instructions' [patent_app_type] => 1 [patent_app_number] => 8/483810 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 55 [patent_no_of_words] => 14346 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 400 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596767.pdf [firstpage_image] =>[orig_patent_app_number] => 483810 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/483810
Programmable data processing system and apparatus for executing both general purpose instructions and special purpose graphic instructions Jun 6, 1995 Issued
Menu