
Alyssa H. Bowler
Examiner (ID: 1245)
| Most Active Art Unit | 2312 |
| Art Unit(s) | 2312, 2303, 2783, 2302 |
| Total Applications | 274 |
| Issued Applications | 225 |
| Pending Applications | 0 |
| Abandoned Applications | 49 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3684938
[patent_doc_number] => 05643683
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-01
[patent_title] => 'Wet type sliding apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/590764
[patent_app_country] => US
[patent_app_date] => 1996-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2695
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/643/05643683.pdf
[firstpage_image] =>[orig_patent_app_number] => 590764
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/590764 | Wet type sliding apparatus | Jan 23, 1996 | Issued |
| 08/399851 | VIDEO DECOMPRESSION AND DECODING SYSTEM UTILIZING CONTROL AND DATA TOKENS | Jun 19, 1995 | Abandoned |
Array
(
[id] => 3667881
[patent_doc_number] => 05625300
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-29
[patent_title] => 'Separate I.sub.DDQ -testing of signal path and bias path in an IC'
[patent_app_type] => 1
[patent_app_number] => 8/355569
[patent_app_country] => US
[patent_app_date] => 1994-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 3757
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/625/05625300.pdf
[firstpage_image] =>[orig_patent_app_number] => 355569
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/355569 | Separate I.sub.DDQ -testing of signal path and bias path in an IC | Dec 13, 1994 | Issued |
Array
(
[id] => 2977301
[patent_doc_number] => 05265235
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-23
[patent_title] => 'Consistency protocols for shared memory multiprocessors'
[patent_app_type] => 1
[patent_app_number] => 8/023854
[patent_app_country] => US
[patent_app_date] => 1993-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 17
[patent_no_of_words] => 19366
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 709
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/265/05265235.pdf
[firstpage_image] =>[orig_patent_app_number] => 023854
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/023854 | Consistency protocols for shared memory multiprocessors | Feb 25, 1993 | Issued |
Array
(
[id] => 2977005
[patent_doc_number] => 05274792
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-28
[patent_title] => 'Information processing apparatus with parallel instruction decoding'
[patent_app_type] => 1
[patent_app_number] => 8/007032
[patent_app_country] => US
[patent_app_date] => 1993-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 3625
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/274/05274792.pdf
[firstpage_image] =>[orig_patent_app_number] => 007032
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/007032 | Information processing apparatus with parallel instruction decoding | Jan 20, 1993 | Issued |
| 07/951926 | CONSISTENCY PROTOCOLS FOR SHARED MEMORY MULTIPROCESSORS | Sep 24, 1992 | Abandoned |
Array
(
[id] => 3047085
[patent_doc_number] => 05301145
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-05
[patent_title] => 'Method and apparatus for recording and reading information, and an information recording element'
[patent_app_type] => 1
[patent_app_number] => 7/936870
[patent_app_country] => US
[patent_app_date] => 1992-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 17
[patent_no_of_words] => 2718
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/301/05301145.pdf
[firstpage_image] =>[orig_patent_app_number] => 936870
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/936870 | Method and apparatus for recording and reading information, and an information recording element | Aug 26, 1992 | Issued |
Array
(
[id] => 2948361
[patent_doc_number] => 05247649
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-21
[patent_title] => 'Multi-processor system having a multi-port cache memory'
[patent_app_type] => 1
[patent_app_number] => 7/933892
[patent_app_country] => US
[patent_app_date] => 1992-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 2501
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/247/05247649.pdf
[firstpage_image] =>[orig_patent_app_number] => 933892
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/933892 | Multi-processor system having a multi-port cache memory | Aug 23, 1992 | Issued |
Array
(
[id] => 2922412
[patent_doc_number] => 05228003
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-13
[patent_title] => 'Semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 7/886348
[patent_app_country] => US
[patent_app_date] => 1992-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 3821
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/228/05228003.pdf
[firstpage_image] =>[orig_patent_app_number] => 886348
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/886348 | Semiconductor memory | May 20, 1992 | Issued |
Array
(
[id] => 2960750
[patent_doc_number] => 05262999
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-16
[patent_title] => 'Large scale integrated circuit for low voltage operation'
[patent_app_type] => 1
[patent_app_number] => 7/838505
[patent_app_country] => US
[patent_app_date] => 1992-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 120
[patent_figures_cnt] => 169
[patent_no_of_words] => 57973
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/262/05262999.pdf
[firstpage_image] =>[orig_patent_app_number] => 838505
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/838505 | Large scale integrated circuit for low voltage operation | Mar 23, 1992 | Issued |
| 07/853027 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREFOR | Mar 17, 1992 | Abandoned |
Array
(
[id] => 2903662
[patent_doc_number] => 05270931
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-14
[patent_title] => 'Software controlled aircraft component configuration system'
[patent_app_type] => 1
[patent_app_number] => 7/852911
[patent_app_country] => US
[patent_app_date] => 1992-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 6263
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/270/05270931.pdf
[firstpage_image] =>[orig_patent_app_number] => 852911
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/852911 | Software controlled aircraft component configuration system | Mar 11, 1992 | Issued |
Array
(
[id] => 2896337
[patent_doc_number] => 05214600
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-25
[patent_title] => 'Semiconductor memory array having interdigitated bit-line structure'
[patent_app_type] => 1
[patent_app_number] => 7/836159
[patent_app_country] => US
[patent_app_date] => 1992-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1397
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/214/05214600.pdf
[firstpage_image] =>[orig_patent_app_number] => 836159
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/836159 | Semiconductor memory array having interdigitated bit-line structure | Feb 23, 1992 | Issued |
Array
(
[id] => 2952790
[patent_doc_number] => 05224069
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-29
[patent_title] => 'Ferroelectric capacitor memory circuit MOS setting and transmission transistors'
[patent_app_type] => 1
[patent_app_number] => 7/832806
[patent_app_country] => US
[patent_app_date] => 1992-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 3695
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 393
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/224/05224069.pdf
[firstpage_image] =>[orig_patent_app_number] => 832806
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/832806 | Ferroelectric capacitor memory circuit MOS setting and transmission transistors | Feb 6, 1992 | Issued |
Array
(
[id] => 2880619
[patent_doc_number] => 05163022
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-10
[patent_title] => 'Semiconductor cell memory with current sensing'
[patent_app_type] => 1
[patent_app_number] => 7/827873
[patent_app_country] => US
[patent_app_date] => 1992-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 56
[patent_figures_cnt] => 81
[patent_no_of_words] => 25501
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/163/05163022.pdf
[firstpage_image] =>[orig_patent_app_number] => 827873
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/827873 | Semiconductor cell memory with current sensing | Jan 29, 1992 | Issued |
Array
(
[id] => 2996139
[patent_doc_number] => 05251177
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-05
[patent_title] => 'Semiconductor memory device having an improved refresh operation'
[patent_app_type] => 1
[patent_app_number] => 7/799925
[patent_app_country] => US
[patent_app_date] => 1991-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 24
[patent_no_of_words] => 5361
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/251/05251177.pdf
[firstpage_image] =>[orig_patent_app_number] => 799925
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/799925 | Semiconductor memory device having an improved refresh operation | Nov 25, 1991 | Issued |
Array
(
[id] => 2973602
[patent_doc_number] => 05265045
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-23
[patent_title] => 'Semiconductor integrated circuit device with built-in memory circuit group'
[patent_app_type] => 1
[patent_app_number] => 7/793315
[patent_app_country] => US
[patent_app_date] => 1991-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 35
[patent_no_of_words] => 8546
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/265/05265045.pdf
[firstpage_image] =>[orig_patent_app_number] => 793315
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/793315 | Semiconductor integrated circuit device with built-in memory circuit group | Nov 14, 1991 | Issued |
Array
(
[id] => 2951430
[patent_doc_number] => 05261072
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-09
[patent_title] => 'Compact disk data transfer system using cache memory'
[patent_app_type] => 1
[patent_app_number] => 7/785486
[patent_app_country] => US
[patent_app_date] => 1991-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 4971
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/261/05261072.pdf
[firstpage_image] =>[orig_patent_app_number] => 785486
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/785486 | Compact disk data transfer system using cache memory | Oct 30, 1991 | Issued |
Array
(
[id] => 3062890
[patent_doc_number] => 05283883
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-01
[patent_title] => 'Method and direct memory access controller for asynchronously reading/writing data from/to a memory with improved throughput'
[patent_app_type] => 1
[patent_app_number] => 7/778507
[patent_app_country] => US
[patent_app_date] => 1991-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 8606
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 512
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/283/05283883.pdf
[firstpage_image] =>[orig_patent_app_number] => 778507
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/778507 | Method and direct memory access controller for asynchronously reading/writing data from/to a memory with improved throughput | Oct 16, 1991 | Issued |
Array
(
[id] => 2948127
[patent_doc_number] => 05260899
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-09
[patent_title] => 'Sense amplifier for semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/767965
[patent_app_country] => US
[patent_app_date] => 1991-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6739
[patent_no_of_claims] => 56
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[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/260/05260899.pdf
[firstpage_image] =>[orig_patent_app_number] => 767965
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/767965 | Sense amplifier for semiconductor memory device | Sep 29, 1991 | Issued |