Search

Alyssa H. Bowler

Examiner (ID: 1245)

Most Active Art Unit
2312
Art Unit(s)
2312, 2303, 2783, 2302
Total Applications
274
Issued Applications
225
Pending Applications
0
Abandoned Applications
49

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2820153 [patent_doc_number] => 05086411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-04 [patent_title] => 'Optical location systems' [patent_app_type] => 1 [patent_app_number] => 7/384696 [patent_app_country] => US [patent_app_date] => 1989-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5260 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/086/05086411.pdf [firstpage_image] =>[orig_patent_app_number] => 384696 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/384696
Optical location systems Jul 24, 1989 Issued
Array ( [id] => 2605387 [patent_doc_number] => 04975879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-04 [patent_title] => 'Biasing scheme for FIFO memories' [patent_app_type] => 1 [patent_app_number] => 7/380369 [patent_app_country] => US [patent_app_date] => 1989-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2552 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/975/04975879.pdf [firstpage_image] =>[orig_patent_app_number] => 380369 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/380369
Biasing scheme for FIFO memories Jul 16, 1989 Issued
07/378799 INFORMATION STORAGE Jul 11, 1989 Abandoned
Array ( [id] => 2889749 [patent_doc_number] => 05159679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-27 [patent_title] => 'Computer system with high speed data transfer capabilities' [patent_app_type] => 1 [patent_app_number] => 7/378579 [patent_app_country] => US [patent_app_date] => 1989-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 17784 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 459 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/159/05159679.pdf [firstpage_image] =>[orig_patent_app_number] => 378579 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/378579
Computer system with high speed data transfer capabilities Jul 9, 1989 Issued
Array ( [id] => 2815505 [patent_doc_number] => 05148393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'MOS dynamic semiconductor memory cell' [patent_app_type] => 1 [patent_app_number] => 7/375909 [patent_app_country] => US [patent_app_date] => 1989-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2648 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/148/05148393.pdf [firstpage_image] =>[orig_patent_app_number] => 375909 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/375909
MOS dynamic semiconductor memory cell Jul 5, 1989 Issued
07/373431 METHOD AND APPARATUS FOR A FILAMENT CHANNEL PASS GATE FERROELECTRIC CAPACITOR MEMORY CELL Jun 29, 1989 Abandoned
Array ( [id] => 2742339 [patent_doc_number] => 05040148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-13 [patent_title] => 'Semiconductor memory device with address transition actuated dummy cell' [patent_app_type] => 1 [patent_app_number] => 7/370869 [patent_app_country] => US [patent_app_date] => 1989-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 10266 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/040/05040148.pdf [firstpage_image] =>[orig_patent_app_number] => 370869 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/370869
Semiconductor memory device with address transition actuated dummy cell Jun 22, 1989 Issued
Array ( [id] => 3086728 [patent_doc_number] => 05297097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Large scale integrated circuit for low voltage operation' [patent_app_type] => 1 [patent_app_number] => 7/366869 [patent_app_country] => US [patent_app_date] => 1989-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 129 [patent_figures_cnt] => 182 [patent_no_of_words] => 58016 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297097.pdf [firstpage_image] =>[orig_patent_app_number] => 366869 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/366869
Large scale integrated circuit for low voltage operation Jun 13, 1989 Issued
Array ( [id] => 2624139 [patent_doc_number] => 04943945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-24 [patent_title] => 'Reference voltage generator for precharging bit lines of a transistor memory' [patent_app_type] => 1 [patent_app_number] => 7/365579 [patent_app_country] => US [patent_app_date] => 1989-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2476 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/943/04943945.pdf [firstpage_image] =>[orig_patent_app_number] => 365579 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/365579
Reference voltage generator for precharging bit lines of a transistor memory Jun 12, 1989 Issued
07/366208 SEMICONDUCTOR MEMORY DEVICE Jun 11, 1989 Abandoned
Array ( [id] => 2682784 [patent_doc_number] => 04984208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-08 [patent_title] => 'Dynamic read/write memory with improved refreshing operation' [patent_app_type] => 1 [patent_app_number] => 7/364529 [patent_app_country] => US [patent_app_date] => 1989-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 91 [patent_no_of_words] => 5558 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/984/04984208.pdf [firstpage_image] =>[orig_patent_app_number] => 364529 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/364529
Dynamic read/write memory with improved refreshing operation Jun 11, 1989 Issued
Array ( [id] => 2812709 [patent_doc_number] => 05140681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Multi-processing system and cache apparatus for use in the same' [patent_app_type] => 1 [patent_app_number] => 7/355680 [patent_app_country] => US [patent_app_date] => 1989-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7061 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/140/05140681.pdf [firstpage_image] =>[orig_patent_app_number] => 355680 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/355680
Multi-processing system and cache apparatus for use in the same May 22, 1989 Issued
Array ( [id] => 2905064 [patent_doc_number] => 05210847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'Noncacheable address random access memory' [patent_app_type] => 1 [patent_app_number] => 7/354513 [patent_app_country] => US [patent_app_date] => 1989-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4227 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210847.pdf [firstpage_image] =>[orig_patent_app_number] => 354513 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/354513
Noncacheable address random access memory May 18, 1989 Issued
Array ( [id] => 2892599 [patent_doc_number] => 05109498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Buffer memory device capable of memorizing operand and instruction data blocks at different block sizes' [patent_app_type] => 1 [patent_app_number] => 7/353361 [patent_app_country] => US [patent_app_date] => 1989-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7050 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/109/05109498.pdf [firstpage_image] =>[orig_patent_app_number] => 353361 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/353361
Buffer memory device capable of memorizing operand and instruction data blocks at different block sizes May 16, 1989 Issued
Array ( [id] => 2754695 [patent_doc_number] => 05023835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-11 [patent_title] => 'Semiconductor memory system for use in logic LSI\'s' [patent_app_type] => 1 [patent_app_number] => 7/351044 [patent_app_country] => US [patent_app_date] => 1989-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5092 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/023/05023835.pdf [firstpage_image] =>[orig_patent_app_number] => 351044 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/351044
Semiconductor memory system for use in logic LSI's May 9, 1989 Issued
07/347222 MULTI-PROCESSOR SYSTEM HAVING A MULTI-PORT CACHE MEMORY May 3, 1989 Abandoned
Array ( [id] => 2818311 [patent_doc_number] => 05148537 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Method and apparatus for effecting an intra-cache data transfer' [patent_app_type] => 1 [patent_app_number] => 7/346470 [patent_app_country] => US [patent_app_date] => 1989-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4900 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/148/05148537.pdf [firstpage_image] =>[orig_patent_app_number] => 346470 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/346470
Method and apparatus for effecting an intra-cache data transfer May 1, 1989 Issued
Array ( [id] => 2889468 [patent_doc_number] => 05109336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Unified working storage management' [patent_app_type] => 1 [patent_app_number] => 7/344715 [patent_app_country] => US [patent_app_date] => 1989-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6694 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/109/05109336.pdf [firstpage_image] =>[orig_patent_app_number] => 344715 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/344715
Unified working storage management Apr 27, 1989 Issued
07/430920 INTEGRATED SEMICONDUCTOR MEMORY AND INTEGRATED SIGNAL PROCESSOR HAVING SUCH A MEMORY Apr 19, 1989 Abandoned
Array ( [id] => 2688736 [patent_doc_number] => 05067078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-19 [patent_title] => 'Cache which provides status information' [patent_app_type] => 1 [patent_app_number] => 7/339464 [patent_app_country] => US [patent_app_date] => 1989-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5965 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/067/05067078.pdf [firstpage_image] =>[orig_patent_app_number] => 339464 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/339464
Cache which provides status information Apr 16, 1989 Issued
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