| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[id] => 2820153
[patent_doc_number] => 05086411
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-04
[patent_title] => 'Optical location systems'
[patent_app_type] => 1
[patent_app_number] => 7/384696
[patent_app_country] => US
[patent_app_date] => 1989-07-25
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[firstpage_image] =>[orig_patent_app_number] => 384696
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Array
(
[id] => 2605387
[patent_doc_number] => 04975879
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[patent_kind] => NA
[patent_issue_date] => 1990-12-04
[patent_title] => 'Biasing scheme for FIFO memories'
[patent_app_type] => 1
[patent_app_number] => 7/380369
[patent_app_country] => US
[patent_app_date] => 1989-07-17
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[pdf_file] => patents/04/975/04975879.pdf
[firstpage_image] =>[orig_patent_app_number] => 380369
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/380369 | Biasing scheme for FIFO memories | Jul 16, 1989 | Issued |
| 07/378799 | INFORMATION STORAGE | Jul 11, 1989 | Abandoned |
Array
(
[id] => 2889749
[patent_doc_number] => 05159679
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-27
[patent_title] => 'Computer system with high speed data transfer capabilities'
[patent_app_type] => 1
[patent_app_number] => 7/378579
[patent_app_country] => US
[patent_app_date] => 1989-07-10
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[firstpage_image] =>[orig_patent_app_number] => 378579
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/378579 | Computer system with high speed data transfer capabilities | Jul 9, 1989 | Issued |
Array
(
[id] => 2815505
[patent_doc_number] => 05148393
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-15
[patent_title] => 'MOS dynamic semiconductor memory cell'
[patent_app_type] => 1
[patent_app_number] => 7/375909
[patent_app_country] => US
[patent_app_date] => 1989-07-06
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/148/05148393.pdf
[firstpage_image] =>[orig_patent_app_number] => 375909
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/375909 | MOS dynamic semiconductor memory cell | Jul 5, 1989 | Issued |
| 07/373431 | METHOD AND APPARATUS FOR A FILAMENT CHANNEL PASS GATE FERROELECTRIC CAPACITOR MEMORY CELL | Jun 29, 1989 | Abandoned |
Array
(
[id] => 2742339
[patent_doc_number] => 05040148
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[patent_kind] => NA
[patent_issue_date] => 1991-08-13
[patent_title] => 'Semiconductor memory device with address transition actuated dummy cell'
[patent_app_type] => 1
[patent_app_number] => 7/370869
[patent_app_country] => US
[patent_app_date] => 1989-06-23
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[pdf_file] => patents/05/040/05040148.pdf
[firstpage_image] =>[orig_patent_app_number] => 370869
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/370869 | Semiconductor memory device with address transition actuated dummy cell | Jun 22, 1989 | Issued |
Array
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[id] => 3086728
[patent_doc_number] => 05297097
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-22
[patent_title] => 'Large scale integrated circuit for low voltage operation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/366869 | Large scale integrated circuit for low voltage operation | Jun 13, 1989 | Issued |
Array
(
[id] => 2624139
[patent_doc_number] => 04943945
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-07-24
[patent_title] => 'Reference voltage generator for precharging bit lines of a transistor memory'
[patent_app_type] => 1
[patent_app_number] => 7/365579
[patent_app_country] => US
[patent_app_date] => 1989-06-13
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[pdf_file] => patents/04/943/04943945.pdf
[firstpage_image] =>[orig_patent_app_number] => 365579
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/365579 | Reference voltage generator for precharging bit lines of a transistor memory | Jun 12, 1989 | Issued |
| 07/366208 | SEMICONDUCTOR MEMORY DEVICE | Jun 11, 1989 | Abandoned |
Array
(
[id] => 2682784
[patent_doc_number] => 04984208
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-08
[patent_title] => 'Dynamic read/write memory with improved refreshing operation'
[patent_app_type] => 1
[patent_app_number] => 7/364529
[patent_app_country] => US
[patent_app_date] => 1989-06-12
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[pdf_file] => patents/04/984/04984208.pdf
[firstpage_image] =>[orig_patent_app_number] => 364529
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/364529 | Dynamic read/write memory with improved refreshing operation | Jun 11, 1989 | Issued |
Array
(
[id] => 2812709
[patent_doc_number] => 05140681
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-18
[patent_title] => 'Multi-processing system and cache apparatus for use in the same'
[patent_app_type] => 1
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[pdf_file] => patents/05/140/05140681.pdf
[firstpage_image] =>[orig_patent_app_number] => 355680
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/355680 | Multi-processing system and cache apparatus for use in the same | May 22, 1989 | Issued |
Array
(
[id] => 2905064
[patent_doc_number] => 05210847
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-11
[patent_title] => 'Noncacheable address random access memory'
[patent_app_type] => 1
[patent_app_number] => 7/354513
[patent_app_country] => US
[patent_app_date] => 1989-05-19
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[firstpage_image] =>[orig_patent_app_number] => 354513
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/354513 | Noncacheable address random access memory | May 18, 1989 | Issued |
Array
(
[id] => 2892599
[patent_doc_number] => 05109498
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-28
[patent_title] => 'Buffer memory device capable of memorizing operand and instruction data blocks at different block sizes'
[patent_app_type] => 1
[patent_app_number] => 7/353361
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[patent_app_date] => 1989-05-17
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[pdf_file] => patents/05/109/05109498.pdf
[firstpage_image] =>[orig_patent_app_number] => 353361
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/353361 | Buffer memory device capable of memorizing operand and instruction data blocks at different block sizes | May 16, 1989 | Issued |
Array
(
[id] => 2754695
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-11
[patent_title] => 'Semiconductor memory system for use in logic LSI\'s'
[patent_app_type] => 1
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[patent_app_country] => US
[patent_app_date] => 1989-05-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/351044 | Semiconductor memory system for use in logic LSI's | May 9, 1989 | Issued |
| 07/347222 | MULTI-PROCESSOR SYSTEM HAVING A MULTI-PORT CACHE MEMORY | May 3, 1989 | Abandoned |
Array
(
[id] => 2818311
[patent_doc_number] => 05148537
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-15
[patent_title] => 'Method and apparatus for effecting an intra-cache data transfer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/346470 | Method and apparatus for effecting an intra-cache data transfer | May 1, 1989 | Issued |
Array
(
[id] => 2889468
[patent_doc_number] => 05109336
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-28
[patent_title] => 'Unified working storage management'
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[patent_app_number] => 7/344715
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[patent_app_date] => 1989-04-28
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[firstpage_image] =>[orig_patent_app_number] => 344715
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/344715 | Unified working storage management | Apr 27, 1989 | Issued |
| 07/430920 | INTEGRATED SEMICONDUCTOR MEMORY AND INTEGRATED SIGNAL PROCESSOR HAVING SUCH A MEMORY | Apr 19, 1989 | Abandoned |
Array
(
[id] => 2688736
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[patent_issue_date] => 1991-11-19
[patent_title] => 'Cache which provides status information'
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[firstpage_image] =>[orig_patent_app_number] => 339464
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/339464 | Cache which provides status information | Apr 16, 1989 | Issued |