
Alyssa H. Bowler
Examiner (ID: 1245)
| Most Active Art Unit | 2312 |
| Art Unit(s) | 2312, 2303, 2783, 2302 |
| Total Applications | 274 |
| Issued Applications | 225 |
| Pending Applications | 0 |
| Abandoned Applications | 49 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
| 07/336817 | SEMICONDUCTOR MEMORY | Apr 12, 1989 | Abandoned |
| 07/337579 | MULTI-STATE EEPROM READ AND WRITE CIRCUITS AND TECHNIQUES | Apr 12, 1989 | Abandoned |
Array
(
[id] => 2944585
[patent_doc_number] => 05197026
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-23
[patent_title] => 'Transparent EEPROM backup of DRAM memories'
[patent_app_type] => 1
[patent_app_number] => 7/337957
[patent_app_country] => US
[patent_app_date] => 1989-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2870
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/197/05197026.pdf
[firstpage_image] =>[orig_patent_app_number] => 337957
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/337957 | Transparent EEPROM backup of DRAM memories | Apr 12, 1989 | Issued |
Array
(
[id] => 2817071
[patent_doc_number] => 05157629
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-20
[patent_title] => 'Selective application of voltages for testing storage cells in semiconductor memory arrangements'
[patent_app_type] => 1
[patent_app_number] => 7/336345
[patent_app_country] => US
[patent_app_date] => 1989-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 6567
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 296
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/157/05157629.pdf
[firstpage_image] =>[orig_patent_app_number] => 336345
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/336345 | Selective application of voltages for testing storage cells in semiconductor memory arrangements | Apr 9, 1989 | Issued |
Array
(
[id] => 3102797
[patent_doc_number] => 05278965
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-11
[patent_title] => 'Direct memory access controller'
[patent_app_type] => 1
[patent_app_number] => 7/332197
[patent_app_country] => US
[patent_app_date] => 1989-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3186
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/278/05278965.pdf
[firstpage_image] =>[orig_patent_app_number] => 332197
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/332197 | Direct memory access controller | Apr 2, 1989 | Issued |
Array
(
[id] => 2998111
[patent_doc_number] => 05267191
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-30
[patent_title] => 'FIFO memory system'
[patent_app_type] => 1
[patent_app_number] => 7/331917
[patent_app_country] => US
[patent_app_date] => 1989-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 23
[patent_no_of_words] => 6065
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/267/05267191.pdf
[firstpage_image] =>[orig_patent_app_number] => 331917
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/331917 | FIFO memory system | Apr 2, 1989 | Issued |
Array
(
[id] => 2945348
[patent_doc_number] => 05233701
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-03
[patent_title] => 'System for managing interprocessor common memory'
[patent_app_type] => 1
[patent_app_number] => 7/330122
[patent_app_country] => US
[patent_app_date] => 1989-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2867
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/233/05233701.pdf
[firstpage_image] =>[orig_patent_app_number] => 330122
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/330122 | System for managing interprocessor common memory | Mar 28, 1989 | Issued |
Array
(
[id] => 2899707
[patent_doc_number] => 05214777
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-25
[patent_title] => 'High speed read/modify/write memory system and method'
[patent_app_type] => 1
[patent_app_number] => 7/328642
[patent_app_country] => US
[patent_app_date] => 1989-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2413
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/214/05214777.pdf
[firstpage_image] =>[orig_patent_app_number] => 328642
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/328642 | High speed read/modify/write memory system and method | Mar 26, 1989 | Issued |
Array
(
[id] => 2787628
[patent_doc_number] => 05151983
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-29
[patent_title] => 'Microcomputer system with selectively bypassed memory output latches'
[patent_app_type] => 1
[patent_app_number] => 7/325803
[patent_app_country] => US
[patent_app_date] => 1989-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 12272
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/151/05151983.pdf
[firstpage_image] =>[orig_patent_app_number] => 325803
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/325803 | Microcomputer system with selectively bypassed memory output latches | Mar 19, 1989 | Issued |
Array
(
[id] => 2819706
[patent_doc_number] => 05086388
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-04
[patent_title] => 'Semiconductor serial/parallel-parallel/serial file memory and storage system'
[patent_app_type] => 1
[patent_app_number] => 7/324823
[patent_app_country] => US
[patent_app_date] => 1989-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 5380
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/086/05086388.pdf
[firstpage_image] =>[orig_patent_app_number] => 324823
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/324823 | Semiconductor serial/parallel-parallel/serial file memory and storage system | Mar 16, 1989 | Issued |
Array
(
[id] => 2708356
[patent_doc_number] => 04989180
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-29
[patent_title] => 'Dynamic memory with logic-in-refresh'
[patent_app_type] => 1
[patent_app_number] => 7/321847
[patent_app_country] => US
[patent_app_date] => 1989-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2496
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/989/04989180.pdf
[firstpage_image] =>[orig_patent_app_number] => 321847
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/321847 | Dynamic memory with logic-in-refresh | Mar 9, 1989 | Issued |
Array
(
[id] => 2795133
[patent_doc_number] => 05142495
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-25
[patent_title] => 'Variable load for margin mode'
[patent_app_type] => 1
[patent_app_number] => 7/321887
[patent_app_country] => US
[patent_app_date] => 1989-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1912
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/142/05142495.pdf
[firstpage_image] =>[orig_patent_app_number] => 321887
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/321887 | Variable load for margin mode | Mar 9, 1989 | Issued |
Array
(
[id] => 2742992
[patent_doc_number] => 05077664
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-31
[patent_title] => 'Direct memory access controller'
[patent_app_type] => 1
[patent_app_number] => 7/318283
[patent_app_country] => US
[patent_app_date] => 1989-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 7602
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/077/05077664.pdf
[firstpage_image] =>[orig_patent_app_number] => 318283
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/318283 | Direct memory access controller | Mar 2, 1989 | Issued |
Array
(
[id] => 2861780
[patent_doc_number] => 05089992
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-18
[patent_title] => 'Semiconductor memory device and a data path using the same'
[patent_app_type] => 1
[patent_app_number] => 7/315377
[patent_app_country] => US
[patent_app_date] => 1989-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 29
[patent_no_of_words] => 7043
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/089/05089992.pdf
[firstpage_image] =>[orig_patent_app_number] => 315377
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/315377 | Semiconductor memory device and a data path using the same | Feb 23, 1989 | Issued |
| 07/315947 | SOFTWARE CONTROLLED AIRCRAFT COMPONENT CONFIGURATION SYSTEM | Feb 22, 1989 | Abandoned |
Array
(
[id] => 2682873
[patent_doc_number] => 04984213
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-08
[patent_title] => 'Memory block address determination circuit'
[patent_app_type] => 1
[patent_app_number] => 7/313237
[patent_app_country] => US
[patent_app_date] => 1989-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7179
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/984/04984213.pdf
[firstpage_image] =>[orig_patent_app_number] => 313237
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/313237 | Memory block address determination circuit | Feb 20, 1989 | Issued |
Array
(
[id] => 2754810
[patent_doc_number] => 05023841
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-11
[patent_title] => 'Double stage sense amplifier for random access memories'
[patent_app_type] => 1
[patent_app_number] => 7/313216
[patent_app_country] => US
[patent_app_date] => 1989-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5234
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/023/05023841.pdf
[firstpage_image] =>[orig_patent_app_number] => 313216
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/313216 | Double stage sense amplifier for random access memories | Feb 20, 1989 | Issued |
Array
(
[id] => 2652386
[patent_doc_number] => 04939693
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-07-03
[patent_title] => 'BiCMOS static memory with improved performance stability'
[patent_app_type] => 1
[patent_app_number] => 7/310796
[patent_app_country] => US
[patent_app_date] => 1989-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9616
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/939/04939693.pdf
[firstpage_image] =>[orig_patent_app_number] => 310796
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/310796 | BiCMOS static memory with improved performance stability | Feb 13, 1989 | Issued |
Array
(
[id] => 2757881
[patent_doc_number] => 05038322
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-06
[patent_title] => 'Method of and device for sub-micron processing a surface'
[patent_app_type] => 1
[patent_app_number] => 7/306367
[patent_app_country] => US
[patent_app_date] => 1989-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 9
[patent_no_of_words] => 6105
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/038/05038322.pdf
[firstpage_image] =>[orig_patent_app_number] => 306367
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/306367 | Method of and device for sub-micron processing a surface | Feb 2, 1989 | Issued |
Array
(
[id] => 2882726
[patent_doc_number] => 05163134
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-10
[patent_title] => 'Method and apparatus for controlling data writing in magnetic recording subsystem'
[patent_app_type] => 1
[patent_app_number] => 7/304519
[patent_app_country] => US
[patent_app_date] => 1989-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1498
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/163/05163134.pdf
[firstpage_image] =>[orig_patent_app_number] => 304519
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/304519 | Method and apparatus for controlling data writing in magnetic recording subsystem | Jan 30, 1989 | Issued |