Search

Alyssa H. Bowler

Examiner (ID: 1245)

Most Active Art Unit
2312
Art Unit(s)
2312, 2303, 2783, 2302
Total Applications
274
Issued Applications
225
Pending Applications
0
Abandoned Applications
49

Applications

Application numberTitle of the applicationFiling DateStatus
07/218736 METHOD AND APPARATUS FOR RECORDING AND READING INFORMATION, AND AN INFORMATION RECORDING ELEMENT Jul 12, 1988 Abandoned
07/218459 CASSETTE LOADING DEVICE Jul 10, 1988 Abandoned
Array ( [id] => 2640446 [patent_doc_number] => 04958318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-18 [patent_title] => 'Sidewall capacitor DRAM cell' [patent_app_type] => 1 [patent_app_number] => 7/216873 [patent_app_country] => US [patent_app_date] => 1988-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 9573 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/958/04958318.pdf [firstpage_image] =>[orig_patent_app_number] => 216873 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/216873
Sidewall capacitor DRAM cell Jul 7, 1988 Issued
Array ( [id] => 2640738 [patent_doc_number] => 04977540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-11 [patent_title] => 'Spin glass type associative processor system' [patent_app_type] => 1 [patent_app_number] => 7/209976 [patent_app_country] => US [patent_app_date] => 1988-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3632 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/977/04977540.pdf [firstpage_image] =>[orig_patent_app_number] => 209976 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/209976
Spin glass type associative processor system Jun 21, 1988 Issued
Array ( [id] => 2664926 [patent_doc_number] => 04972380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-20 [patent_title] => 'Decoding circuit for functional block' [patent_app_type] => 1 [patent_app_number] => 7/206416 [patent_app_country] => US [patent_app_date] => 1988-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 5171 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/972/04972380.pdf [firstpage_image] =>[orig_patent_app_number] => 206416 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/206416
Decoding circuit for functional block Jun 13, 1988 Issued
Array ( [id] => 2598565 [patent_doc_number] => 04970687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-13 [patent_title] => 'Semiconductor memory device having a timing generator circuit which provides a write pulse signal which has an optional timing relationship with the chip select signal' [patent_app_type] => 1 [patent_app_number] => 7/203936 [patent_app_country] => US [patent_app_date] => 1988-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 10233 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/970/04970687.pdf [firstpage_image] =>[orig_patent_app_number] => 203936 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/203936
Semiconductor memory device having a timing generator circuit which provides a write pulse signal which has an optional timing relationship with the chip select signal Jun 7, 1988 Issued
Array ( [id] => 2853972 [patent_doc_number] => 05138573 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-11 [patent_title] => 'Non-volatile storage cell' [patent_app_type] => 1 [patent_app_number] => 7/203266 [patent_app_country] => US [patent_app_date] => 1988-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 6199 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/138/05138573.pdf [firstpage_image] =>[orig_patent_app_number] => 203266 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/203266
Non-volatile storage cell Jun 6, 1988 Issued
07/185406 SEMICONDUCTOR MEMORY INCLUDING AN ARRANGEMENT TO PERMIT EXTERNAL MONITORING OF AN INTERNAL CONTROL SIGNAL Apr 24, 1988 Issued
Array ( [id] => 2572384 [patent_doc_number] => 04945517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-31 [patent_title] => 'Dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 7/184256 [patent_app_country] => US [patent_app_date] => 1988-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2858 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/945/04945517.pdf [firstpage_image] =>[orig_patent_app_number] => 184256 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/184256
Dynamic random access memory Apr 20, 1988 Issued
Array ( [id] => 2742346 [patent_doc_number] => 05033023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-16 [patent_title] => 'High density EEPROM cell and process for making the cell' [patent_app_type] => 1 [patent_app_number] => 7/179196 [patent_app_country] => US [patent_app_date] => 1988-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7242 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/033/05033023.pdf [firstpage_image] =>[orig_patent_app_number] => 179196 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/179196
High density EEPROM cell and process for making the cell Apr 7, 1988 Issued
Array ( [id] => 2859384 [patent_doc_number] => 05105384 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-14 [patent_title] => 'Low current semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/178166 [patent_app_country] => US [patent_app_date] => 1988-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5814 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/105/05105384.pdf [firstpage_image] =>[orig_patent_app_number] => 178166 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/178166
Low current semiconductor memory device Apr 5, 1988 Issued
07/155668 CACHED RANDOM ACCESS MEMORY DEVICE AND SYSTEM Feb 11, 1988 Abandoned
Array ( [id] => 2877676 [patent_doc_number] => 05097442 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-17 [patent_title] => 'Programmable depth first-in, first-out memory' [patent_app_type] => 1 [patent_app_number] => 7/146526 [patent_app_country] => US [patent_app_date] => 1988-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5290 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/097/05097442.pdf [firstpage_image] =>[orig_patent_app_number] => 146526 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/146526
Programmable depth first-in, first-out memory Jan 20, 1988 Issued
Array ( [id] => 2815686 [patent_doc_number] => 05115500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-19 [patent_title] => 'Plural incompatible instruction format decode method and apparatus' [patent_app_type] => 1 [patent_app_number] => 7/142585 [patent_app_country] => US [patent_app_date] => 1988-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4681 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/115/05115500.pdf [firstpage_image] =>[orig_patent_app_number] => 142585 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/142585
Plural incompatible instruction format decode method and apparatus Jan 10, 1988 Issued
Array ( [id] => 2725375 [patent_doc_number] => 05053997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-01 [patent_title] => 'Dynamic random access memory with FET equalization of bit lines' [patent_app_type] => 1 [patent_app_number] => 7/132646 [patent_app_country] => US [patent_app_date] => 1987-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8040 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/053/05053997.pdf [firstpage_image] =>[orig_patent_app_number] => 132646 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/132646
Dynamic random access memory with FET equalization of bit lines Dec 7, 1987 Issued
07/119766 SEMICONDUCTOR MEMORY DEVICE Nov 11, 1987 Abandoned
07/112946 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH BUILT-IN MEMORY CIRCUIT GROUP Oct 26, 1987 Abandoned
Array ( [id] => 2702811 [patent_doc_number] => 04996648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-26 [patent_title] => 'Neural network using random binary code' [patent_app_type] => 1 [patent_app_number] => 7/113636 [patent_app_country] => US [patent_app_date] => 1987-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3152 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/996/04996648.pdf [firstpage_image] =>[orig_patent_app_number] => 113636 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/113636
Neural network using random binary code Oct 26, 1987 Issued
Array ( [id] => 2698328 [patent_doc_number] => 05050124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-17 [patent_title] => 'Semiconductor memory having load transistor circuit' [patent_app_type] => 1 [patent_app_number] => 7/094706 [patent_app_country] => US [patent_app_date] => 1987-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7139 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/050/05050124.pdf [firstpage_image] =>[orig_patent_app_number] => 094706 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/094706
Semiconductor memory having load transistor circuit Sep 8, 1987 Issued
07/079066 SEMICONDUCTOR MEMORY DEVICE Jul 28, 1987 Abandoned
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