Search

Alyssa H. Bowler

Examiner (ID: 1245)

Most Active Art Unit
2312
Art Unit(s)
2312, 2303, 2783, 2302
Total Applications
274
Issued Applications
225
Pending Applications
0
Abandoned Applications
49

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2946918 [patent_doc_number] => 05220667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-15 [patent_title] => 'Computer system' [patent_app_type] => 1 [patent_app_number] => 7/584606 [patent_app_country] => US [patent_app_date] => 1990-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2395 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/220/05220667.pdf [firstpage_image] =>[orig_patent_app_number] => 584606 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/584606
Computer system Sep 18, 1990 Issued
Array ( [id] => 2958682 [patent_doc_number] => 05255381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-19 [patent_title] => 'Mode switching for a memory system with diagnostic scan' [patent_app_type] => 1 [patent_app_number] => 7/582476 [patent_app_country] => US [patent_app_date] => 1990-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 12035 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/255/05255381.pdf [firstpage_image] =>[orig_patent_app_number] => 582476 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/582476
Mode switching for a memory system with diagnostic scan Sep 13, 1990 Issued
Array ( [id] => 2896992 [patent_doc_number] => 05269009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'Processor system with improved memory transfer means' [patent_app_type] => 1 [patent_app_number] => 7/577344 [patent_app_country] => US [patent_app_date] => 1990-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3206 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/269/05269009.pdf [firstpage_image] =>[orig_patent_app_number] => 577344 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/577344
Processor system with improved memory transfer means Sep 3, 1990 Issued
Array ( [id] => 2817009 [patent_doc_number] => 05146576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-08 [patent_title] => 'Managing high speed slow access channel to slow speed cyclic system data transfer' [patent_app_type] => 1 [patent_app_number] => 7/575748 [patent_app_country] => US [patent_app_date] => 1990-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4195 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/146/05146576.pdf [firstpage_image] =>[orig_patent_app_number] => 575748 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/575748
Managing high speed slow access channel to slow speed cyclic system data transfer Aug 30, 1990 Issued
Array ( [id] => 2889727 [patent_doc_number] => 05159678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-27 [patent_title] => 'Method for efficient non-virtual main memory management' [patent_app_type] => 1 [patent_app_number] => 7/572045 [patent_app_country] => US [patent_app_date] => 1990-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6138 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/159/05159678.pdf [firstpage_image] =>[orig_patent_app_number] => 572045 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/572045
Method for efficient non-virtual main memory management Aug 22, 1990 Issued
07/571045 HIERARCHICAL MULTI-DATA LINES DRAM ARRAY ARCHITECTURE WITH HIGH SPEED SENSING CIRCUIT Aug 21, 1990 Abandoned
07/568864 INFORMATION PROCESSING APPARATUS Aug 16, 1990 Abandoned
Array ( [id] => 2679837 [patent_doc_number] => 05047980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-10 [patent_title] => 'BiCMOS memory having memory cells connected directly to address decoders' [patent_app_type] => 1 [patent_app_number] => 7/569673 [patent_app_country] => US [patent_app_date] => 1990-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3644 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/047/05047980.pdf [firstpage_image] =>[orig_patent_app_number] => 569673 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/569673
BiCMOS memory having memory cells connected directly to address decoders Aug 16, 1990 Issued
Array ( [id] => 2716853 [patent_doc_number] => 05014240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-07 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/569597 [patent_app_country] => US [patent_app_date] => 1990-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 3922 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/014/05014240.pdf [firstpage_image] =>[orig_patent_app_number] => 569597 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/569597
Semiconductor memory device Aug 13, 1990 Issued
07/564563 SUBSTRATE FOR RECORDING MEDIUM, RECORDING MEDIUM, METHOD FOR PREPARING THE SAME, RECORDING AND REPRODUCING DEVICE, AND RECORDING, REPRODUCING AND ERASING METHOD BY USE OF SUCH RECORDING MEDIUM Aug 8, 1990 Abandoned
Array ( [id] => 2988740 [patent_doc_number] => 05226147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Semiconductor memory device for simple cache system' [patent_app_type] => 1 [patent_app_number] => 7/564657 [patent_app_country] => US [patent_app_date] => 1990-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9179 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226147.pdf [firstpage_image] =>[orig_patent_app_number] => 564657 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/564657
Semiconductor memory device for simple cache system Aug 8, 1990 Issued
Array ( [id] => 2863828 [patent_doc_number] => 05126972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-30 [patent_title] => 'Arrangement and method of ascertaining memory addresses which have been accessed during program execution' [patent_app_type] => 1 [patent_app_number] => 7/565025 [patent_app_country] => US [patent_app_date] => 1990-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3378 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/126/05126972.pdf [firstpage_image] =>[orig_patent_app_number] => 565025 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/565025
Arrangement and method of ascertaining memory addresses which have been accessed during program execution Aug 7, 1990 Issued
Array ( [id] => 2863768 [patent_doc_number] => 05126969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-30 [patent_title] => 'Integrated circuit including non-volatile memory cell capable of temporarily holding information' [patent_app_type] => 1 [patent_app_number] => 7/563193 [patent_app_country] => US [patent_app_date] => 1990-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1509 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/126/05126969.pdf [firstpage_image] =>[orig_patent_app_number] => 563193 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/563193
Integrated circuit including non-volatile memory cell capable of temporarily holding information Aug 5, 1990 Issued
Array ( [id] => 2804211 [patent_doc_number] => 05136718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-04 [patent_title] => 'Communications arrangement for digital data processing system employing heterogeneous multiple processing nodes' [patent_app_type] => 1 [patent_app_number] => 7/563960 [patent_app_country] => US [patent_app_date] => 1990-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6073 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/136/05136718.pdf [firstpage_image] =>[orig_patent_app_number] => 563960 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/563960
Communications arrangement for digital data processing system employing heterogeneous multiple processing nodes Aug 5, 1990 Issued
Array ( [id] => 2847398 [patent_doc_number] => 05121355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Integrated semiconductor memory and signal processor' [patent_app_type] => 1 [patent_app_number] => 7/563737 [patent_app_country] => US [patent_app_date] => 1990-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2724 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/121/05121355.pdf [firstpage_image] =>[orig_patent_app_number] => 563737 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/563737
Integrated semiconductor memory and signal processor Aug 2, 1990 Issued
Array ( [id] => 2795488 [patent_doc_number] => 05165029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-17 [patent_title] => 'Cache memory with test function' [patent_app_type] => 1 [patent_app_number] => 7/558929 [patent_app_country] => US [patent_app_date] => 1990-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6620 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/165/05165029.pdf [firstpage_image] =>[orig_patent_app_number] => 558929 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/558929
Cache memory with test function Jul 26, 1990 Issued
Array ( [id] => 2902602 [patent_doc_number] => 05210716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'Semiconductor nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 7/557403 [patent_app_country] => US [patent_app_date] => 1990-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1501 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210716.pdf [firstpage_image] =>[orig_patent_app_number] => 557403 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/557403
Semiconductor nonvolatile memory Jul 22, 1990 Issued
Array ( [id] => 2678514 [patent_doc_number] => 05073872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'Data output control circuit for semiconductor storage device' [patent_app_type] => 1 [patent_app_number] => 7/551303 [patent_app_country] => US [patent_app_date] => 1990-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3548 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073872.pdf [firstpage_image] =>[orig_patent_app_number] => 551303 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/551303
Data output control circuit for semiconductor storage device Jul 11, 1990 Issued
Array ( [id] => 2996491 [patent_doc_number] => 05212666 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-18 [patent_title] => 'Memory apparatus having flexibly designed memory capacity' [patent_app_type] => 1 [patent_app_number] => 7/551449 [patent_app_country] => US [patent_app_date] => 1990-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6404 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/212/05212666.pdf [firstpage_image] =>[orig_patent_app_number] => 551449 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/551449
Memory apparatus having flexibly designed memory capacity Jul 9, 1990 Issued
Array ( [id] => 2800628 [patent_doc_number] => 05136533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-04 [patent_title] => 'Sidewall capacitor DRAM cell' [patent_app_type] => 1 [patent_app_number] => 7/551557 [patent_app_country] => US [patent_app_date] => 1990-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 9550 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/136/05136533.pdf [firstpage_image] =>[orig_patent_app_number] => 551557 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/551557
Sidewall capacitor DRAM cell Jul 9, 1990 Issued
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