
Alyssa H. Bowler
Examiner (ID: 1245)
| Most Active Art Unit | 2312 |
| Art Unit(s) | 2312, 2303, 2783, 2302 |
| Total Applications | 274 |
| Issued Applications | 225 |
| Pending Applications | 0 |
| Abandoned Applications | 49 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2776384
[patent_doc_number] => 05036489
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-30
[patent_title] => 'Compact expandable folded first-in-first-out queue'
[patent_app_type] => 1
[patent_app_number] => 7/515303
[patent_app_country] => US
[patent_app_date] => 1990-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 9024
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/036/05036489.pdf
[firstpage_image] =>[orig_patent_app_number] => 515303
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/515303 | Compact expandable folded first-in-first-out queue | Apr 26, 1990 | Issued |
Array
(
[id] => 2734782
[patent_doc_number] => 05058060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-15
[patent_title] => 'Optical memory cell'
[patent_app_type] => 1
[patent_app_number] => 7/511888
[patent_app_country] => US
[patent_app_date] => 1990-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2329
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 320
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/058/05058060.pdf
[firstpage_image] =>[orig_patent_app_number] => 511888
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/511888 | Optical memory cell | Apr 18, 1990 | Issued |
Array
(
[id] => 2851054
[patent_doc_number] => 05172338
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-15
[patent_title] => 'Multi-state EEprom read and write circuits and techniques'
[patent_app_type] => 1
[patent_app_number] => 7/508273
[patent_app_country] => US
[patent_app_date] => 1990-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 33
[patent_no_of_words] => 12659
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 16
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/172/05172338.pdf
[firstpage_image] =>[orig_patent_app_number] => 508273
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/508273 | Multi-state EEprom read and write circuits and techniques | Apr 10, 1990 | Issued |
Array
(
[id] => 2706965
[patent_doc_number] => 04989106
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-29
[patent_title] => 'Cassette loading device with pull-in mechanism'
[patent_app_type] => 1
[patent_app_number] => 7/512084
[patent_app_country] => US
[patent_app_date] => 1990-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 24
[patent_no_of_words] => 12935
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/989/04989106.pdf
[firstpage_image] =>[orig_patent_app_number] => 512084
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/512084 | Cassette loading device with pull-in mechanism | Apr 10, 1990 | Issued |
Array
(
[id] => 2785689
[patent_doc_number] => 05132928
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-21
[patent_title] => 'Divided word line type non-volatile semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/501703
[patent_app_country] => US
[patent_app_date] => 1990-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 10483
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/132/05132928.pdf
[firstpage_image] =>[orig_patent_app_number] => 501703
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/501703 | Divided word line type non-volatile semiconductor memory device | Mar 29, 1990 | Issued |
| 07/501793 | SEMICONDUCTOR MEMORY ARRAY HAVING INTERDIGITATED BIT-LINE STRUCTURE | Mar 29, 1990 | Abandoned |
Array
(
[id] => 2907744
[patent_doc_number] => 05241641
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-31
[patent_title] => 'Hierarchical cache memory apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/501256
[patent_app_country] => US
[patent_app_date] => 1990-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 47
[patent_no_of_words] => 23793
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 604
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/241/05241641.pdf
[firstpage_image] =>[orig_patent_app_number] => 501256
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/501256 | Hierarchical cache memory apparatus | Mar 27, 1990 | Issued |
Array
(
[id] => 2951305
[patent_doc_number] => 05261066
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-09
[patent_title] => 'Data processing system and method with small fully-associative cache and prefetch buffers'
[patent_app_type] => 1
[patent_app_number] => 7/499958
[patent_app_country] => US
[patent_app_date] => 1990-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 22
[patent_no_of_words] => 9222
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/261/05261066.pdf
[firstpage_image] =>[orig_patent_app_number] => 499958
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/499958 | Data processing system and method with small fully-associative cache and prefetch buffers | Mar 26, 1990 | Issued |
Array
(
[id] => 2755081
[patent_doc_number] => 05003509
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-03-26
[patent_title] => 'Multi-port, bipolar-CMOS memory cell'
[patent_app_type] => 1
[patent_app_number] => 7/500083
[patent_app_country] => US
[patent_app_date] => 1990-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2413
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/003/05003509.pdf
[firstpage_image] =>[orig_patent_app_number] => 500083
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/500083 | Multi-port, bipolar-CMOS memory cell | Mar 26, 1990 | Issued |
| 07/498773 | HIGH EFFICIENCY CHARGE PUMP CIRCUIT | Mar 25, 1990 | Issued |
Array
(
[id] => 2989841
[patent_doc_number] => 05257360
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-26
[patent_title] => 'Re-configurable block length cache'
[patent_app_type] => 1
[patent_app_number] => 7/497967
[patent_app_country] => US
[patent_app_date] => 1990-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3322
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/257/05257360.pdf
[firstpage_image] =>[orig_patent_app_number] => 497967
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/497967 | Re-configurable block length cache | Mar 22, 1990 | Issued |
Array
(
[id] => 2742368
[patent_doc_number] => 05040149
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-13
[patent_title] => 'Semiconductor memory with divided readout from storage'
[patent_app_type] => 1
[patent_app_number] => 7/496076
[patent_app_country] => US
[patent_app_date] => 1990-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 5210
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/040/05040149.pdf
[firstpage_image] =>[orig_patent_app_number] => 496076
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/496076 | Semiconductor memory with divided readout from storage | Mar 14, 1990 | Issued |
| 07/493898 | APPARATUS AND METHOD FOR PROVIDING A STALL CACHE | Mar 14, 1990 | Abandoned |
Array
(
[id] => 2790669
[patent_doc_number] => 05088062
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-11
[patent_title] => 'Memory device having common data lines for reading and writing'
[patent_app_type] => 1
[patent_app_number] => 7/493683
[patent_app_country] => US
[patent_app_date] => 1990-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4466
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/088/05088062.pdf
[firstpage_image] =>[orig_patent_app_number] => 493683
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/493683 | Memory device having common data lines for reading and writing | Mar 14, 1990 | Issued |
| 07/493433 | SEMICONDUCTOR MEMORY DEVICE HAVING INFORMATION INDICATIVE OF PRESENCE OF DEFECTIVE MEMORY CELL | Mar 13, 1990 | Abandoned |
Array
(
[id] => 2827104
[patent_doc_number] => 05081610
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-14
[patent_title] => 'Reference cell for reading EEPROM memory devices'
[patent_app_type] => 1
[patent_app_number] => 7/491903
[patent_app_country] => US
[patent_app_date] => 1990-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 3204
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/081/05081610.pdf
[firstpage_image] =>[orig_patent_app_number] => 491903
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/491903 | Reference cell for reading EEPROM memory devices | Mar 11, 1990 | Issued |
Array
(
[id] => 2889856
[patent_doc_number] => 05109357
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-28
[patent_title] => 'DRAM memory cell and method of operation thereof for transferring increased amount of charge to a bit line'
[patent_app_type] => 1
[patent_app_number] => 7/491180
[patent_app_country] => US
[patent_app_date] => 1990-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 3398
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/109/05109357.pdf
[firstpage_image] =>[orig_patent_app_number] => 491180
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/491180 | DRAM memory cell and method of operation thereof for transferring increased amount of charge to a bit line | Mar 8, 1990 | Issued |
Array
(
[id] => 2930943
[patent_doc_number] => 05206942
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-27
[patent_title] => 'Partially storing control circuit used in a memory unit'
[patent_app_type] => 1
[patent_app_number] => 7/490447
[patent_app_country] => US
[patent_app_date] => 1990-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5847
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/206/05206942.pdf
[firstpage_image] =>[orig_patent_app_number] => 490447
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/490447 | Partially storing control circuit used in a memory unit | Mar 7, 1990 | Issued |
Array
(
[id] => 2743525
[patent_doc_number] => 05077692
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-31
[patent_title] => 'Information storage device with batch select capability'
[patent_app_type] => 1
[patent_app_number] => 7/489203
[patent_app_country] => US
[patent_app_date] => 1990-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4035
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/077/05077692.pdf
[firstpage_image] =>[orig_patent_app_number] => 489203
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/489203 | Information storage device with batch select capability | Mar 4, 1990 | Issued |
Array
(
[id] => 2682790
[patent_doc_number] => 05027324
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-25
[patent_title] => 'Sense amplifier driver for use in memory device'
[patent_app_type] => 1
[patent_app_number] => 7/485913
[patent_app_country] => US
[patent_app_date] => 1990-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3386
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/027/05027324.pdf
[firstpage_image] =>[orig_patent_app_number] => 485913
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/485913 | Sense amplifier driver for use in memory device | Feb 26, 1990 | Issued |