Search

Alyssa H. Bowler

Examiner (ID: 1245)

Most Active Art Unit
2312
Art Unit(s)
2312, 2303, 2783, 2302
Total Applications
274
Issued Applications
225
Pending Applications
0
Abandoned Applications
49

Applications

Application numberTitle of the applicationFiling DateStatus
07/454289 ON-CHIP/OFF-CHIP MEMORY SWITCHING USING SYSTEM CONFIGURATION BIT Dec 20, 1989 Abandoned
Array ( [id] => 2885914 [patent_doc_number] => 05185721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'Charge-retaining signal boosting circuit and method' [patent_app_type] => 1 [patent_app_number] => 7/453335 [patent_app_country] => US [patent_app_date] => 1989-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 3060 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185721.pdf [firstpage_image] =>[orig_patent_app_number] => 453335 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/453335
Charge-retaining signal boosting circuit and method Dec 18, 1989 Issued
Array ( [id] => 2762141 [patent_doc_number] => 05072378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-10 [patent_title] => 'Direct access storage device with independently stored parity' [patent_app_type] => 1 [patent_app_number] => 7/452674 [patent_app_country] => US [patent_app_date] => 1989-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 17637 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/072/05072378.pdf [firstpage_image] =>[orig_patent_app_number] => 452674 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/452674
Direct access storage device with independently stored parity Dec 17, 1989 Issued
Array ( [id] => 2678394 [patent_doc_number] => 04954991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-04 [patent_title] => 'Semiconductor memory with p-channel load transistor' [patent_app_type] => 1 [patent_app_number] => 7/447391 [patent_app_country] => US [patent_app_date] => 1989-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7146 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/954/04954991.pdf [firstpage_image] =>[orig_patent_app_number] => 447391 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/447391
Semiconductor memory with p-channel load transistor Dec 6, 1989 Issued
07/446855 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH BUILT-IN MEMORY CIRCUIT GROUP Dec 5, 1989 Abandoned
Array ( [id] => 2869914 [patent_doc_number] => 05083295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-21 [patent_title] => 'Integrated memory circuit with interconnected sense amplifiers' [patent_app_type] => 1 [patent_app_number] => 7/444929 [patent_app_country] => US [patent_app_date] => 1989-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3034 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/083/05083295.pdf [firstpage_image] =>[orig_patent_app_number] => 444929 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/444929
Integrated memory circuit with interconnected sense amplifiers Nov 29, 1989 Issued
Array ( [id] => 2830430 [patent_doc_number] => 05168464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-01 [patent_title] => 'Nonvolatile differential memory device and method' [patent_app_type] => 1 [patent_app_number] => 7/442809 [patent_app_country] => US [patent_app_date] => 1989-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2952 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/168/05168464.pdf [firstpage_image] =>[orig_patent_app_number] => 442809 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/442809
Nonvolatile differential memory device and method Nov 28, 1989 Issued
Array ( [id] => 2682809 [patent_doc_number] => 05027325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-25 [patent_title] => 'Semiconductor memory device having circuit for reading-out and writing-in of data' [patent_app_type] => 1 [patent_app_number] => 7/440480 [patent_app_country] => US [patent_app_date] => 1989-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4036 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/027/05027325.pdf [firstpage_image] =>[orig_patent_app_number] => 440480 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/440480
Semiconductor memory device having circuit for reading-out and writing-in of data Nov 20, 1989 Issued
Array ( [id] => 2688918 [patent_doc_number] => 05005157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-02 [patent_title] => 'Apparatus for selectively providing RAS signals or RAS timing and coded RAS address signals' [patent_app_type] => 1 [patent_app_number] => 7/436143 [patent_app_country] => US [patent_app_date] => 1989-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2192 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/005/05005157.pdf [firstpage_image] =>[orig_patent_app_number] => 436143 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/436143
Apparatus for selectively providing RAS signals or RAS timing and coded RAS address signals Nov 12, 1989 Issued
Array ( [id] => 2779255 [patent_doc_number] => 04985871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-15 [patent_title] => 'Memory controller for using reserved dram addresses for expanded memory space' [patent_app_type] => 1 [patent_app_number] => 7/435323 [patent_app_country] => US [patent_app_date] => 1989-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1936 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/985/04985871.pdf [firstpage_image] =>[orig_patent_app_number] => 435323 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/435323
Memory controller for using reserved dram addresses for expanded memory space Nov 12, 1989 Issued
Array ( [id] => 2605260 [patent_doc_number] => 04975872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-04 [patent_title] => 'Dual port memory device with tag bit marking' [patent_app_type] => 1 [patent_app_number] => 7/435049 [patent_app_country] => US [patent_app_date] => 1989-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3380 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/975/04975872.pdf [firstpage_image] =>[orig_patent_app_number] => 435049 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/435049
Dual port memory device with tag bit marking Nov 12, 1989 Issued
Array ( [id] => 2798561 [patent_doc_number] => 05142671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-25 [patent_title] => 'Plural cache architecture for real time multitasking' [patent_app_type] => 1 [patent_app_number] => 7/434046 [patent_app_country] => US [patent_app_date] => 1989-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3424 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/142/05142671.pdf [firstpage_image] =>[orig_patent_app_number] => 434046 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/434046
Plural cache architecture for real time multitasking Nov 8, 1989 Issued
07/431667 FLOPPY DISK CONTROLLER WITH DMA VERIFY OPERATIONS Nov 2, 1989 Abandoned
Array ( [id] => 2913874 [patent_doc_number] => 05218686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-08 [patent_title] => 'Combined synchronous and asynchronous memory controller' [patent_app_type] => 1 [patent_app_number] => 7/431656 [patent_app_country] => US [patent_app_date] => 1989-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9288 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/218/05218686.pdf [firstpage_image] =>[orig_patent_app_number] => 431656 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/431656
Combined synchronous and asynchronous memory controller Nov 2, 1989 Issued
Array ( [id] => 2565017 [patent_doc_number] => 04961164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-02 [patent_title] => 'Semiconductor memory device with dual selection circuitry including CMOS and bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 7/430907 [patent_app_country] => US [patent_app_date] => 1989-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9324 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/961/04961164.pdf [firstpage_image] =>[orig_patent_app_number] => 430907 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/430907
Semiconductor memory device with dual selection circuitry including CMOS and bipolar transistors Oct 30, 1989 Issued
Array ( [id] => 2833923 [patent_doc_number] => 05170373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-08 [patent_title] => 'Three transistor EEPROM cell' [patent_app_type] => 1 [patent_app_number] => 7/429308 [patent_app_country] => US [patent_app_date] => 1989-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3510 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/170/05170373.pdf [firstpage_image] =>[orig_patent_app_number] => 429308 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/429308
Three transistor EEPROM cell Oct 30, 1989 Issued
07/429527 SEMICONDUCTOR MEMORY AND VIDEO SIGNAL PROCESSING CIRCUIT HAVING THE SAME Oct 30, 1989 Abandoned
Array ( [id] => 2758611 [patent_doc_number] => 05031149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-09 [patent_title] => 'Non-volatile semiconductor memory device having, at the prestage of an address decoder, a level shifter for generating a program voltage' [patent_app_type] => 1 [patent_app_number] => 7/425947 [patent_app_country] => US [patent_app_date] => 1989-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5677 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/031/05031149.pdf [firstpage_image] =>[orig_patent_app_number] => 425947 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/425947
Non-volatile semiconductor memory device having, at the prestage of an address decoder, a level shifter for generating a program voltage Oct 23, 1989 Issued
Array ( [id] => 2735085 [patent_doc_number] => 05058076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-15 [patent_title] => 'Address control circuit for data memory employed in signal delay circuit' [patent_app_type] => 1 [patent_app_number] => 7/424557 [patent_app_country] => US [patent_app_date] => 1989-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3604 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/058/05058076.pdf [firstpage_image] =>[orig_patent_app_number] => 424557 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/424557
Address control circuit for data memory employed in signal delay circuit Oct 19, 1989 Issued
Array ( [id] => 2708338 [patent_doc_number] => 04989179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-29 [patent_title] => 'High density integrated circuit analog signal recording and playback system' [patent_app_type] => 1 [patent_app_number] => 7/420296 [patent_app_country] => US [patent_app_date] => 1989-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7091 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/989/04989179.pdf [firstpage_image] =>[orig_patent_app_number] => 420296 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/420296
High density integrated circuit analog signal recording and playback system Oct 11, 1989 Issued
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