| Application number | Title of the application | Filing Date | Status |
|---|
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Array
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[patent_issue_date] => 1991-11-05
[patent_title] => 'Reprogrammable logic fuse based on a 6-device SRAM cell for logic arrays'
[patent_app_type] => 1
[patent_app_number] => 7/414339
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Array
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[patent_issue_date] => 1991-02-26
[patent_title] => 'Zero standby power, radiation hardened, memory redundancy circuit'
[patent_app_type] => 1
[patent_app_number] => 7/414889
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[patent_app_date] => 1989-09-28
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| 07/407189 | SERIAL INPUT/OUTPUT SEMICONDUCTOR MEMORY | Sep 13, 1989 | Abandoned |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/401343 | Non-bus request refresh system for shortening refresh timing | Aug 30, 1989 | Issued |
Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/398815 | Direct memory access controller | Aug 24, 1989 | Issued |
| 07/396042 | RANDOM ACCESS MEMORY | Aug 20, 1989 | Abandoned |
| 07/395834 | EEPROM MEMORY SYSTEM HAVING SELECTABLE PROGRAMMING VOLTAGE FOR LOW POWER READABILITY | Aug 17, 1989 | Abandoned |
Array
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