Search

Alyssa H. Bowler

Examiner (ID: 1245)

Most Active Art Unit
2312
Art Unit(s)
2312, 2303, 2783, 2302
Total Applications
274
Issued Applications
225
Pending Applications
0
Abandoned Applications
49

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2717415 [patent_doc_number] => 05062081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-29 [patent_title] => 'Multiport memory collision/detection circuitry' [patent_app_type] => 1 [patent_app_number] => 7/419019 [patent_app_country] => US [patent_app_date] => 1989-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4014 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/062/05062081.pdf [firstpage_image] =>[orig_patent_app_number] => 419019 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/419019
Multiport memory collision/detection circuitry Oct 9, 1989 Issued
Array ( [id] => 2678552 [patent_doc_number] => 05073874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'Method of and apparatus for reducing current of semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/417127 [patent_app_country] => US [patent_app_date] => 1989-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 5739 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073874.pdf [firstpage_image] =>[orig_patent_app_number] => 417127 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/417127
Method of and apparatus for reducing current of semiconductor memory device Oct 3, 1989 Issued
Array ( [id] => 2773277 [patent_doc_number] => 05063537 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-05 [patent_title] => 'Reprogrammable logic fuse based on a 6-device SRAM cell for logic arrays' [patent_app_type] => 1 [patent_app_number] => 7/414339 [patent_app_country] => US [patent_app_date] => 1989-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 8008 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/063/05063537.pdf [firstpage_image] =>[orig_patent_app_number] => 414339 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/414339
Reprogrammable logic fuse based on a 6-device SRAM cell for logic arrays Sep 28, 1989 Issued
Array ( [id] => 2703260 [patent_doc_number] => 04996670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-26 [patent_title] => 'Zero standby power, radiation hardened, memory redundancy circuit' [patent_app_type] => 1 [patent_app_number] => 7/414889 [patent_app_country] => US [patent_app_date] => 1989-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2207 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/996/04996670.pdf [firstpage_image] =>[orig_patent_app_number] => 414889 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/414889
Zero standby power, radiation hardened, memory redundancy circuit Sep 27, 1989 Issued
07/407189 SERIAL INPUT/OUTPUT SEMICONDUCTOR MEMORY Sep 13, 1989 Abandoned
Array ( [id] => 2861419 [patent_doc_number] => 05134563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-28 [patent_title] => 'Sequentially processing data in a cached data storage system' [patent_app_type] => 1 [patent_app_number] => 7/407078 [patent_app_country] => US [patent_app_date] => 1989-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 9359 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/134/05134563.pdf [firstpage_image] =>[orig_patent_app_number] => 407078 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/407078
Sequentially processing data in a cached data storage system Sep 13, 1989 Issued
Array ( [id] => 2769200 [patent_doc_number] => 05060145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-22 [patent_title] => 'Memory access system for pipelined data paths to and from storage' [patent_app_type] => 1 [patent_app_number] => 7/403624 [patent_app_country] => US [patent_app_date] => 1989-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4504 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/060/05060145.pdf [firstpage_image] =>[orig_patent_app_number] => 403624 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/403624
Memory access system for pipelined data paths to and from storage Sep 5, 1989 Issued
Array ( [id] => 2904103 [patent_doc_number] => 05177705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-05 [patent_title] => 'Programming of an electrically-erasable, electrically-programmable, read-only memory array' [patent_app_type] => 1 [patent_app_number] => 7/402399 [patent_app_country] => US [patent_app_date] => 1989-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/177/05177705.pdf [firstpage_image] =>[orig_patent_app_number] => 402399 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/402399
Programming of an electrically-erasable, electrically-programmable, read-only memory array Sep 4, 1989 Issued
Array ( [id] => 2818275 [patent_doc_number] => 05148535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Non-bus request refresh system for shortening refresh timing' [patent_app_type] => 1 [patent_app_number] => 7/401343 [patent_app_country] => US [patent_app_date] => 1989-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2023 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/148/05148535.pdf [firstpage_image] =>[orig_patent_app_number] => 401343 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/401343
Non-bus request refresh system for shortening refresh timing Aug 30, 1989 Issued
Array ( [id] => 2640701 [patent_doc_number] => 04977538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-11 [patent_title] => 'Semiconductor memory device having hierarchical row selecting lines' [patent_app_type] => 1 [patent_app_number] => 7/400223 [patent_app_country] => US [patent_app_date] => 1989-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8280 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/977/04977538.pdf [firstpage_image] =>[orig_patent_app_number] => 400223 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/400223
Semiconductor memory device having hierarchical row selecting lines Aug 28, 1989 Issued
Array ( [id] => 2753596 [patent_doc_number] => 05029142 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'Static memory device provided with a signal generating circuit for high-speed precharge' [patent_app_type] => 1 [patent_app_number] => 7/400309 [patent_app_country] => US [patent_app_date] => 1989-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3402 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/029/05029142.pdf [firstpage_image] =>[orig_patent_app_number] => 400309 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/400309
Static memory device provided with a signal generating circuit for high-speed precharge Aug 28, 1989 Issued
Array ( [id] => 2757618 [patent_doc_number] => 05031097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-09 [patent_title] => 'Direct memory access controller' [patent_app_type] => 1 [patent_app_number] => 7/398815 [patent_app_country] => US [patent_app_date] => 1989-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3891 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/031/05031097.pdf [firstpage_image] =>[orig_patent_app_number] => 398815 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/398815
Direct memory access controller Aug 24, 1989 Issued
07/396042 RANDOM ACCESS MEMORY Aug 20, 1989 Abandoned
07/395834 EEPROM MEMORY SYSTEM HAVING SELECTABLE PROGRAMMING VOLTAGE FOR LOW POWER READABILITY Aug 17, 1989 Abandoned
Array ( [id] => 2758628 [patent_doc_number] => 05031150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-09 [patent_title] => 'Control circuit for a semiconductor memory device and semiconductor memory system' [patent_app_type] => 1 [patent_app_number] => 7/393784 [patent_app_country] => US [patent_app_date] => 1989-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 7325 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/031/05031150.pdf [firstpage_image] =>[orig_patent_app_number] => 393784 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/393784
Control circuit for a semiconductor memory device and semiconductor memory system Aug 14, 1989 Issued
Array ( [id] => 2865350 [patent_doc_number] => 05084838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-28 [patent_title] => 'Large-scale integrated circuit device such as a wafer scale memory having improved arrangements for bypassing, redundancy, and unit integrated circuit interconnection' [patent_app_type] => 1 [patent_app_number] => 7/391783 [patent_app_country] => US [patent_app_date] => 1989-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 19332 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/084/05084838.pdf [firstpage_image] =>[orig_patent_app_number] => 391783 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/391783
Large-scale integrated circuit device such as a wafer scale memory having improved arrangements for bypassing, redundancy, and unit integrated circuit interconnection Aug 8, 1989 Issued
Array ( [id] => 2743485 [patent_doc_number] => 05077690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-31 [patent_title] => 'Memory input data test arrangement' [patent_app_type] => 1 [patent_app_number] => 7/391059 [patent_app_country] => US [patent_app_date] => 1989-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4525 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/077/05077690.pdf [firstpage_image] =>[orig_patent_app_number] => 391059 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/391059
Memory input data test arrangement Aug 8, 1989 Issued
Array ( [id] => 2989427 [patent_doc_number] => 05204840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-20 [patent_title] => 'Means and methods for preserving microprocessor memory' [patent_app_type] => 1 [patent_app_number] => 7/391096 [patent_app_country] => US [patent_app_date] => 1989-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3527 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/204/05204840.pdf [firstpage_image] =>[orig_patent_app_number] => 391096 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/391096
Means and methods for preserving microprocessor memory Aug 7, 1989 Issued
Array ( [id] => 2715929 [patent_doc_number] => 04992980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-12 [patent_title] => 'Novel architecture for virtual ground high-density EPROMS' [patent_app_type] => 1 [patent_app_number] => 7/390159 [patent_app_country] => US [patent_app_date] => 1989-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4117 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/992/04992980.pdf [firstpage_image] =>[orig_patent_app_number] => 390159 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/390159
Novel architecture for virtual ground high-density EPROMS Aug 6, 1989 Issued
Array ( [id] => 2823641 [patent_doc_number] => 05079742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-07 [patent_title] => 'Read-only-memory having sectional output lines with related memory elements responsive to early and late-occurring input signals' [patent_app_type] => 1 [patent_app_number] => 7/386849 [patent_app_country] => US [patent_app_date] => 1989-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2799 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/079/05079742.pdf [firstpage_image] =>[orig_patent_app_number] => 386849 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/386849
Read-only-memory having sectional output lines with related memory elements responsive to early and late-occurring input signals Jul 27, 1989 Issued
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