Amanda C. Abrahamson

Array ( [id] => 4283003 [patent_doc_number] => 06281589 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'System of selectively cleaning copper substrate surfaces, in-situ, to remove copper oxides' [patent_app_type] => 1 [patent_app_number] => 9/270901 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5730 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281589.pdf [firstpage_image] =>[orig_patent_app_number] => 270901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1463609 [patent_doc_number] => 06350993 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'High speed composite p-channel Si/SiGe heterostructure for field effect devices' [patent_app_type] => B1 [patent_app_number] => 09/267323 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 7482 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350993.pdf [firstpage_image] =>[orig_patent_app_number] => 09267323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4243630 [patent_doc_number] => 06166395 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Amorphous silicon interconnect with multiple silicon layers' [patent_app_type] => 1 [patent_app_number] => 9/260183 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3126 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166395.pdf [firstpage_image] =>[orig_patent_app_number] => 260183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4387215 [patent_doc_number] => 06294807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers' [patent_app_type] => 1 [patent_app_number] => 9/259001 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2575 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294807.pdf [firstpage_image] =>[orig_patent_app_number] => 259001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4090751 [patent_doc_number] => 06025628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'High breakdown voltage twin well device with source/drain regions widely spaced from fox regions' [patent_app_type] => 1 [patent_app_number] => 9/253291 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 3890 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025628.pdf [firstpage_image] =>[orig_patent_app_number] => 253291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4101728 [patent_doc_number] => 06097070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'MOSFET structure and process for low gate induced drain leakage (GILD)' [patent_app_type] => 1 [patent_app_number] => 9/250881 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2882 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097070.pdf [firstpage_image] =>[orig_patent_app_number] => 250881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4137421 [patent_doc_number] => 06147372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Layout of an image sensor for increasing photon induced current' [patent_app_type] => 1 [patent_app_number] => 9/246293 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2592 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147372.pdf [firstpage_image] =>[orig_patent_app_number] => 246293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4282065 [patent_doc_number] => 06281522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method of manufacturing a semiconductor and a semiconductor light-emitting device' [patent_app_type] => 1 [patent_app_number] => 9/243462 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8059 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281522.pdf [firstpage_image] =>[orig_patent_app_number] => 243462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4414258 [patent_doc_number] => 06229185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'CMOS integrated circuit for lessening latch-up susceptibility' [patent_app_type] => 1 [patent_app_number] => 9/241493 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2030 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229185.pdf [firstpage_image] =>[orig_patent_app_number] => 241493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4414376 [patent_doc_number] => 06265771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Dual chip with heat sink' [patent_app_type] => 1 [patent_app_number] => 9/238492 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1976 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265771.pdf [firstpage_image] =>[orig_patent_app_number] => 238492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4257409 [patent_doc_number] => 06207999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Double coding mask read only memory (mask ROM) for minimizing band-to-band leakage' [patent_app_type] => 1 [patent_app_number] => 9/238381 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3278 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207999.pdf [firstpage_image] =>[orig_patent_app_number] => 238381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4190635 [patent_doc_number] => 06160300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Multi-layer gate conductor having a diffusion barrier in the bottom layer' [patent_app_type] => 1 [patent_app_number] => 9/238081 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4054 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160300.pdf [firstpage_image] =>[orig_patent_app_number] => 238081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363302 [patent_doc_number] => 06169292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Thin film type monolithic semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/233481 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 5676 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169292.pdf [firstpage_image] =>[orig_patent_app_number] => 233481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4243691 [patent_doc_number] => 06166399 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Active matrix device including thin film transistors' [patent_app_type] => 1 [patent_app_number] => 9/233143 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6226 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166399.pdf [firstpage_image] =>[orig_patent_app_number] => 233143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4412803 [patent_doc_number] => 06239464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Semiconductor gate trench with covered open ends' [patent_app_type] => 1 [patent_app_number] => 9/226720 [patent_app_country] => US [patent_app_date] => 1999-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 33 [patent_no_of_words] => 4256 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239464.pdf [firstpage_image] =>[orig_patent_app_number] => 226720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4385491 [patent_doc_number] => 06303962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures' [patent_app_type] => 1 [patent_app_number] => 9/227512 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 6074 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303962.pdf [firstpage_image] =>[orig_patent_app_number] => 227512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6221860 [patent_doc_number] => 20020003254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'NVRAM CELL WITH PLANAR CONTROL GATE' [patent_app_type] => new [patent_app_number] => 09/225182 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2119 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003254.pdf [firstpage_image] =>[orig_patent_app_number] => 09225182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4137381 [patent_doc_number] => 06147369 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'SCR and current divider structure of electrostatic discharge protective circuit' [patent_app_type] => 1 [patent_app_number] => 9/223652 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2249 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147369.pdf [firstpage_image] =>[orig_patent_app_number] => 223652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1471643 [patent_doc_number] => 06407441 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Integrated circuit and method of using porous silicon to achieve component isolation in radio frequency applications' [patent_app_type] => B1 [patent_app_number] => 09/215700 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4318 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407441.pdf [firstpage_image] =>[orig_patent_app_number] => 09215700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4089415 [patent_doc_number] => 06163045 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Reduced parasitic leakage in semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/215011 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4332 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163045.pdf [firstpage_image] =>[orig_patent_app_number] => 215011 [rel_patent_id] =>[rel_patent_doc_number] =>)