Amanda C. Abrahamson

Array ( [id] => 7375148 [patent_doc_number] => 20040178402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Multi-terminal device having logic functional' [patent_app_type] => new [patent_app_number] => 10/761022 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13190 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20040178402.pdf [firstpage_image] =>[orig_patent_app_number] => 10761022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7283582 [patent_doc_number] => 20040144973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Agglomeration elimination for metal sputter deposition of chalcogenides' [patent_app_type] => new [patent_app_number] => 10/758008 [patent_app_country] => US [patent_app_date] => 2004-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5317 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20040144973.pdf [firstpage_image] =>[orig_patent_app_number] => 10758008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 681129 [patent_doc_number] => 07084496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Method and apparatus for providing optoelectronic communication with an electronic device' [patent_app_type] => utility [patent_app_number] => 10/757206 [patent_app_country] => US [patent_app_date] => 2004-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5568 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084496.pdf [firstpage_image] =>[orig_patent_app_number] => 10757206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7304998 [patent_doc_number] => 20040140567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Semiconductor device and method of manufacture thereof' [patent_app_type] => new [patent_app_number] => 10/756012 [patent_app_country] => US [patent_app_date] => 2004-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5288 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20040140567.pdf [firstpage_image] =>[orig_patent_app_number] => 10756012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 683015 [patent_doc_number] => 07081656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'CMOS constructions' [patent_app_type] => utility [patent_app_number] => 10/757252 [patent_app_country] => US [patent_app_date] => 2004-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6669 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/081/07081656.pdf [firstpage_image] =>[orig_patent_app_number] => 10757252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7283661 [patent_doc_number] => 20040145052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Semiconductor device and display device using the same' [patent_app_type] => new [patent_app_number] => 10/756121 [patent_app_country] => US [patent_app_date] => 2004-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9649 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20040145052.pdf [firstpage_image] =>[orig_patent_app_number] => 10756121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7314311 [patent_doc_number] => 20040222487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Semiconductor device having a shielding layer' [patent_app_type] => new [patent_app_number] => 10/753081 [patent_app_country] => US [patent_app_date] => 2004-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3972 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20040222487.pdf [firstpage_image] =>[orig_patent_app_number] => 10753081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 700178 [patent_doc_number] => 07067873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Charge trapping device' [patent_app_type] => utility [patent_app_number] => 10/753948 [patent_app_country] => US [patent_app_date] => 2004-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9010 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/067/07067873.pdf [firstpage_image] =>[orig_patent_app_number] => 10753948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7448679 [patent_doc_number] => 20040164422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Semiconductor integrated circuit having pads layout for increasing signal integrity and reducing chip size' [patent_app_type] => new [patent_app_number] => 10/750942 [patent_app_country] => US [patent_app_date] => 2004-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2490 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20040164422.pdf [firstpage_image] =>[orig_patent_app_number] => 10750942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7154434 [patent_doc_number] => 20050082623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'System for integrating a circuit on an isolation layer and method thereof' [patent_app_type] => utility [patent_app_number] => 10/750752 [patent_app_country] => US [patent_app_date] => 2004-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20050082623.pdf [firstpage_image] =>[orig_patent_app_number] => 10750752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1009723 [patent_doc_number] => 06900485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Unit pixel in CMOS image sensor with enhanced reset efficiency' [patent_app_type] => utility [patent_app_number] => 10/746042 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4784 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900485.pdf [firstpage_image] =>[orig_patent_app_number] => 10746042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7219622 [patent_doc_number] => 20040155291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Electrostatic discharge device' [patent_app_type] => new [patent_app_number] => 10/743651 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14350 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20040155291.pdf [firstpage_image] =>[orig_patent_app_number] => 10743651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 959029 [patent_doc_number] => 06953975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/731152 [patent_app_country] => US [patent_app_date] => 2003-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 8030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/953/06953975.pdf [firstpage_image] =>[orig_patent_app_number] => 10731152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7677548 [patent_doc_number] => 20040152278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Low dielectric constant STI with SOI devices' [patent_app_type] => new [patent_app_number] => 10/730641 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8768 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20040152278.pdf [firstpage_image] =>[orig_patent_app_number] => 10730641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 681101 [patent_doc_number] => 07084479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Line level air gaps' [patent_app_type] => utility [patent_app_number] => 10/731377 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 2643 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084479.pdf [firstpage_image] =>[orig_patent_app_number] => 10731377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7301214 [patent_doc_number] => 20040113191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Memory circuitry and mehtod of forming memory circuitry' [patent_app_type] => new [patent_app_number] => 10/728977 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2676 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20040113191.pdf [firstpage_image] =>[orig_patent_app_number] => 10728977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7058969 [patent_doc_number] => 20050001328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Dual chips stacked packaging structure' [patent_app_type] => utility [patent_app_number] => 10/726577 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1826 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001328.pdf [firstpage_image] =>[orig_patent_app_number] => 10726577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7456698 [patent_doc_number] => 20040119107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Fabrication method and structure of semiconductor non-volatile memory device' [patent_app_type] => new [patent_app_number] => 10/726507 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15781 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20040119107.pdf [firstpage_image] =>[orig_patent_app_number] => 10726507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7094867 [patent_doc_number] => 20050127475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'APPARATUS AND METHOD FOR ELECTRONIC FUSE WITH IMPROVED ESD TOLERANCE' [patent_app_type] => utility [patent_app_number] => 10/707282 [patent_app_country] => US [patent_app_date] => 2003-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2933 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20050127475.pdf [firstpage_image] =>[orig_patent_app_number] => 10707282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 738846 [patent_doc_number] => 07034357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Insulated gate semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/724825 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5858 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/034/07034357.pdf [firstpage_image] =>[orig_patent_app_number] => 10724825 [rel_patent_id] =>[rel_patent_doc_number] =>)