Search

Amanda C Walke

Examiner (ID: 16999, Phone: (571)272-1337 , Office: P/1722 )

Most Active Art Unit
1722
Art Unit(s)
1752, 1722, 1737, 1795
Total Applications
2637
Issued Applications
2172
Pending Applications
129
Abandoned Applications
336

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15257913 [patent_doc_number] => 20190377690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => Method and Apparatus for Vector Permutation [patent_app_type] => utility [patent_app_number] => 16/551587 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551587 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/551587
Method and apparatus for vector permutation Aug 25, 2019 Issued
Array ( [id] => 15257913 [patent_doc_number] => 20190377690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => Method and Apparatus for Vector Permutation [patent_app_type] => utility [patent_app_number] => 16/551587 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551587 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/551587
Method and apparatus for vector permutation Aug 25, 2019 Issued
Array ( [id] => 15257913 [patent_doc_number] => 20190377690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => Method and Apparatus for Vector Permutation [patent_app_type] => utility [patent_app_number] => 16/551587 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551587 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/551587
Method and apparatus for vector permutation Aug 25, 2019 Issued
Array ( [id] => 15257913 [patent_doc_number] => 20190377690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => Method and Apparatus for Vector Permutation [patent_app_type] => utility [patent_app_number] => 16/551587 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551587 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/551587
Method and apparatus for vector permutation Aug 25, 2019 Issued
Array ( [id] => 15982147 [patent_doc_number] => 10671401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-02 [patent_title] => Memory hierarchy to transfer vector data for operators of a directed acyclic graph [patent_app_type] => utility [patent_app_number] => 16/542571 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9442 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542571 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542571
Memory hierarchy to transfer vector data for operators of a directed acyclic graph Aug 15, 2019 Issued
Array ( [id] => 17069260 [patent_doc_number] => 20210271476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => METHOD FOR ACCELERATING THE EXECUTION OF A SINGLE-PATH PROGRAM BY THE PARALLEL EXECUTION OF CONDITIONALLY CONCURRENT SEQUENCES [patent_app_type] => utility [patent_app_number] => 17/260852 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6156 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17260852 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/260852
METHOD FOR ACCELERATING THE EXECUTION OF A SINGLE-PATH PROGRAM BY THE PARALLEL EXECUTION OF CONDITIONALLY CONCURRENT SEQUENCES Jul 14, 2019 Abandoned
Array ( [id] => 15935725 [patent_doc_number] => 20200159496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => SYSTOLIC RANDOM NUMBER GENERATOR [patent_app_type] => utility [patent_app_number] => 16/459080 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16459080 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/459080
Systolic random number generator Jun 30, 2019 Issued
Array ( [id] => 16543293 [patent_doc_number] => 20200409708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => Heterogeneous cpuid spoofing for remote processors [patent_app_type] => utility [patent_app_number] => 16/453531 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453531 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453531
Heterogeneous CPUID spoofing for remote processors Jun 25, 2019 Issued
Array ( [id] => 16894962 [patent_doc_number] => 11036515 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-15 [patent_title] => System and method for instruction unwinding in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 16/447470 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 23224 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447470 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447470
System and method for instruction unwinding in an out-of-order processor Jun 19, 2019 Issued
Array ( [id] => 16802013 [patent_doc_number] => 10996957 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-04 [patent_title] => System and method for instruction mapping in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 16/447431 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 23124 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447431 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447431
System and method for instruction mapping in an out-of-order processor Jun 19, 2019 Issued
Array ( [id] => 17364908 [patent_doc_number] => 11231929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => One-dimensional zero padding in a stream of matrix elements [patent_app_type] => utility [patent_app_number] => 16/420447 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 49 [patent_no_of_words] => 36721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420447 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/420447
One-dimensional zero padding in a stream of matrix elements May 22, 2019 Issued
Array ( [id] => 14840393 [patent_doc_number] => 20190278597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => Inserting Null Vectors nto a Stream of Vectors [patent_app_type] => utility [patent_app_number] => 16/420467 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420467 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/420467
Inserting null vectors into a stream of vectors May 22, 2019 Issued
Array ( [id] => 17408877 [patent_doc_number] => 11249759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Two-dimensional zero padding in a stream of matrix elements [patent_app_type] => utility [patent_app_number] => 16/420457 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 49 [patent_no_of_words] => 36736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420457 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/420457
Two-dimensional zero padding in a stream of matrix elements May 22, 2019 Issued
Array ( [id] => 16565767 [patent_doc_number] => 10891136 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-12 [patent_title] => Data transmission between memory and on chip memory of inference engine for machine learning via a single data gathering instruction [patent_app_type] => utility [patent_app_number] => 16/420103 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2701 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420103 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/420103
Data transmission between memory and on chip memory of inference engine for machine learning via a single data gathering instruction May 21, 2019 Issued
Array ( [id] => 14750619 [patent_doc_number] => 20190258483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => SELECTING PROCESSING BASED ON EXPECTED VALUE OF SELECTED CHARACTER [patent_app_type] => utility [patent_app_number] => 16/401131 [patent_app_country] => US [patent_app_date] => 2019-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16401131 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/401131
Selecting processing based on expected value of selected character May 1, 2019 Issued
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16/401134
Selecting processing based on expected value of selected character May 1, 2019 Issued
Array ( [id] => 16986906 [patent_doc_number] => 11074078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Adjustment of load access size by a multi-threaded, self-scheduling processor to manage network congestion [patent_app_type] => utility [patent_app_number] => 16/399748 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 25186 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399748 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399748
Adjustment of load access size by a multi-threaded, self-scheduling processor to manage network congestion Apr 29, 2019 Issued
Array ( [id] => 16346146 [patent_doc_number] => 20200310797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR SWIZZLE OPERATIONS IN A CONFIGURABLE SPATIAL ACCELERATOR [patent_app_type] => utility [patent_app_number] => 16/370915 [patent_app_country] => US [patent_app_date] => 2019-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 96393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370915 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370915
Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator Mar 29, 2019 Issued
Array ( [id] => 17515699 [patent_doc_number] => 11294850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => System, apparatus and method for increasing bandwidth of edge-located agents of an integrated circuit [patent_app_type] => utility [patent_app_number] => 16/369220 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7073 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369220 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/369220
System, apparatus and method for increasing bandwidth of edge-located agents of an integrated circuit Mar 28, 2019 Issued
Array ( [id] => 17423059 [patent_doc_number] => 11256513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Indirect control flow instructions and inhibiting data value speculation [patent_app_type] => utility [patent_app_number] => 17/043921 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 11405 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17043921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/043921
Indirect control flow instructions and inhibiting data value speculation Mar 13, 2019 Issued
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