Search

Amanda C Walke

Examiner (ID: 16999, Phone: (571)272-1337 , Office: P/1722 )

Most Active Art Unit
1722
Art Unit(s)
1752, 1722, 1737, 1795
Total Applications
2637
Issued Applications
2172
Pending Applications
129
Abandoned Applications
336

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13467151 [patent_doc_number] => 20180285118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => RECONFIGURABLE PROCESSOR WITH LOAD-STORE SLICES SUPPORTING REORDER AND CONTROLLING ACCESS TO CACHE SLICES [patent_app_type] => utility [patent_app_number] => 16/001333 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001333 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001333
Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices Jun 5, 2018 Issued
Array ( [id] => 18577480 [patent_doc_number] => 11734011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-22 [patent_title] => Context partitioning of branch prediction structures [patent_app_type] => utility [patent_app_number] => 15/968389 [patent_app_country] => US [patent_app_date] => 2018-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8251 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15968389 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/968389
Context partitioning of branch prediction structures Apr 30, 2018 Issued
Array ( [id] => 13212647 [patent_doc_number] => 10120693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Fast multi-width instruction issue in parallel slice processor [patent_app_type] => utility [patent_app_number] => 15/939367 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15939367 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/939367
Fast multi-width instruction issue in parallel slice processor Mar 28, 2018 Issued
Array ( [id] => 13171773 [patent_doc_number] => 10102001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Parallel slice processor shadowing states of hardware threads across execution slices [patent_app_type] => utility [patent_app_number] => 15/938987 [patent_app_country] => US [patent_app_date] => 2018-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8831 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15938987 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/938987
Parallel slice processor shadowing states of hardware threads across execution slices Mar 27, 2018 Issued
Array ( [id] => 14539025 [patent_doc_number] => 20190205134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => TRANSMITTING STATION [patent_app_type] => utility [patent_app_number] => 16/314926 [patent_app_country] => US [patent_app_date] => 2018-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16314926 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/314926
Transmitting station for detecting state change of data stored in memory Mar 18, 2018 Issued
Array ( [id] => 14395467 [patent_doc_number] => 10311017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Reconfigurable processor and timing control method thereof [patent_app_type] => utility [patent_app_number] => 15/922511 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5878 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15922511 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/922511
Reconfigurable processor and timing control method thereof Mar 14, 2018 Issued
Array ( [id] => 13130217 [patent_doc_number] => 10083039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices [patent_app_type] => utility [patent_app_number] => 15/883601 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15883601 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/883601
Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices Jan 29, 2018 Issued
Array ( [id] => 12756199 [patent_doc_number] => 20180143900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => MICROCOMPUTER HAVING PROCESSOR CAPABLE OF CHANGING ENDIAN BASED ON ENDIAN INFORMATION IN MEMORY [patent_app_type] => utility [patent_app_number] => 15/876780 [patent_app_country] => US [patent_app_date] => 2018-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876780 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/876780
Microcomputer having processor capable of changing endian based on endian information in memory Jan 21, 2018 Issued
Array ( [id] => 12756268 [patent_doc_number] => 20180143923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => Providing State Storage in a Processor for System Management Mode [patent_app_type] => utility [patent_app_number] => 15/873089 [patent_app_country] => US [patent_app_date] => 2018-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873089 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/873089
Providing State Storage in a Processor for System Management Mode Jan 16, 2018 Abandoned
Array ( [id] => 17408872 [patent_doc_number] => 11249754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Apparatus and method for vector horizontal add of signed/unsigned words and doublewords [patent_app_type] => utility [patent_app_number] => 15/850131 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 13147 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850131 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/850131
Apparatus and method for vector horizontal add of signed/unsigned words and doublewords Dec 20, 2017 Issued
Array ( [id] => 12869719 [patent_doc_number] => 20180181748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => HARDWARE MONITOR OF A PROCESSING UNIT STACK STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/847827 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15847827 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/847827
Stack overflow protection by monitoring addresses of a stack of multi-bit protection codes Dec 18, 2017 Issued
Array ( [id] => 13240749 [patent_doc_number] => 10133573 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-20 [patent_title] => Multivalue reductions using serial initial reductions in multiple register spaces and parallel subsequent reductions in a single register space [patent_app_type] => utility [patent_app_number] => 15/839637 [patent_app_country] => US [patent_app_date] => 2017-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5176 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839637 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/839637
Multivalue reductions using serial initial reductions in multiple register spaces and parallel subsequent reductions in a single register space Dec 11, 2017 Issued
Array ( [id] => 14457513 [patent_doc_number] => 10324717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Selecting processing based on expected value of selected character [patent_app_type] => utility [patent_app_number] => 15/825802 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 21275 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825802 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825802
Selecting processing based on expected value of selected character Nov 28, 2017 Issued
Array ( [id] => 12571041 [patent_doc_number] => 10019265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Selectively blocking branch prediction for a predetermined number of instructions [patent_app_type] => utility [patent_app_number] => 15/818810 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7952 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15818810 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/818810
Selectively blocking branch prediction for a predetermined number of instructions Nov 20, 2017 Issued
Array ( [id] => 13003847 [patent_doc_number] => 10025592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Selectively blocking branch prediction for a predetermined number of instructions [patent_app_type] => utility [patent_app_number] => 15/818808 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7886 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15818808 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/818808
Selectively blocking branch prediction for a predetermined number of instructions Nov 20, 2017 Issued
Array ( [id] => 13511899 [patent_doc_number] => 20180307492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => SYSTEM AND METHOD OF REDUCING PROCESSOR PIPELINE STALL CAUSED BY FULL LOAD QUEUE [patent_app_type] => utility [patent_app_number] => 15/810835 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810835 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/810835
System and method of reducing processor pipeline stall caused by full load queue Nov 12, 2017 Issued
Array ( [id] => 14235089 [patent_doc_number] => 20190129717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => EFFICIENT MANAGEMENT OF SCRATCH REGISTERS [patent_app_type] => utility [patent_app_number] => 15/800321 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800321 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/800321
Suppress unnecessary mapping for scratch register Oct 31, 2017 Issued
Array ( [id] => 13120319 [patent_doc_number] => 10078513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-18 [patent_title] => Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements [patent_app_type] => utility [patent_app_number] => 15/799033 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 15569 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799033 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799033
Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements Oct 30, 2017 Issued
Array ( [id] => 13467131 [patent_doc_number] => 20180285108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => BRANCH PREDICTION USING A PERCEPTRON-BASED BRANCH PREDICTION TECHNIQUE [patent_app_type] => utility [patent_app_number] => 15/794436 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794436 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/794436
BRANCH PREDICTION USING A PERCEPTRON-BASED BRANCH PREDICTION TECHNIQUE Oct 25, 2017 Abandoned
Array ( [id] => 16607900 [patent_doc_number] => 10908903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Efficiency for coordinated start interpretive execution exit for a multithreaded processor [patent_app_type] => utility [patent_app_number] => 15/717279 [patent_app_country] => US [patent_app_date] => 2017-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8652 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15717279 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/717279
Efficiency for coordinated start interpretive execution exit for a multithreaded processor Sep 26, 2017 Issued
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