Search

Amanda C Walke

Examiner (ID: 16999, Phone: (571)272-1337 , Office: P/1722 )

Most Active Art Unit
1722
Art Unit(s)
1752, 1722, 1737, 1795
Total Applications
2637
Issued Applications
2172
Pending Applications
129
Abandoned Applications
336

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14457511 [patent_doc_number] => 10324716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Selecting processing based on expected value of selected character [patent_app_type] => utility [patent_app_number] => 15/449219 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 21255 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449219 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/449219
Selecting processing based on expected value of selected character Mar 2, 2017 Issued
Array ( [id] => 16338114 [patent_doc_number] => 10789069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Dynamically selecting version of instruction to be executed [patent_app_type] => utility [patent_app_number] => 15/449183 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 21080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449183 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/449183
Dynamically selecting version of instruction to be executed Mar 2, 2017 Issued
Array ( [id] => 12986038 [patent_doc_number] => 20170344373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => DISTANCE-BASED BRANCH PREDICTION AND DETECTION [patent_app_type] => utility [patent_app_number] => 15/440383 [patent_app_country] => US [patent_app_date] => 2017-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15440383 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/440383
DISTANCE-BASED BRANCH PREDICTION AND DETECTION Feb 22, 2017 Abandoned
Array ( [id] => 14061777 [patent_doc_number] => 10235181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Out-of-order processor and method for back to back instruction issue [patent_app_type] => utility [patent_app_number] => 15/424682 [patent_app_country] => US [patent_app_date] => 2017-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3771 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15424682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/424682
Out-of-order processor and method for back to back instruction issue Feb 2, 2017 Issued
Array ( [id] => 11823888 [patent_doc_number] => 20170212825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'HARDWARE PROFILING MECHANISM TO ENABLE PAGE LEVEL AUTOMATIC BINARY TRANSLATION' [patent_app_type] => utility [patent_app_number] => 15/403120 [patent_app_country] => US [patent_app_date] => 2017-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403120 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/403120
HARDWARE PROFILING MECHANISM TO ENABLE PAGE LEVEL AUTOMATIC BINARY TRANSLATION Jan 9, 2017 Abandoned
Array ( [id] => 14009335 [patent_doc_number] => 10223126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Out-of-order processor and method for back to back instruction issue [patent_app_type] => utility [patent_app_number] => 15/399938 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3771 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399938 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399938
Out-of-order processor and method for back to back instruction issue Jan 5, 2017 Issued
Array ( [id] => 12891655 [patent_doc_number] => 20180189060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => WAIT AND POLL INSTRUCTIONS FOR MONITORING A PLURALITY OF ADDRESSES [patent_app_type] => utility [patent_app_number] => 15/394432 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15394432 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/394432
Wait and poll instructions for monitoring a plurality of addresses Dec 28, 2016 Issued
Array ( [id] => 12845083 [patent_doc_number] => 20180173534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => Branch Predictor with Branch Resolution Code Injection [patent_app_type] => utility [patent_app_number] => 15/385011 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385011 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385011
Branch Predictor with Branch Resolution Code Injection Dec 19, 2016 Abandoned
Array ( [id] => 11931551 [patent_doc_number] => 09798549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-24 [patent_title] => 'Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction' [patent_app_type] => utility [patent_app_number] => 15/338691 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4431 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338691 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/338691
Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction Oct 30, 2016 Issued
Array ( [id] => 13767277 [patent_doc_number] => 10175980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Neural network compute tile [patent_app_type] => utility [patent_app_number] => 15/335769 [patent_app_country] => US [patent_app_date] => 2016-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15335769 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/335769
Neural network compute tile Oct 26, 2016 Issued
Array ( [id] => 13226529 [patent_doc_number] => 10127040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Processor and method for executing memory access and computing instructions for host matrix operations [patent_app_type] => utility [patent_app_number] => 15/279217 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5847 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279217 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/279217
Processor and method for executing memory access and computing instructions for host matrix operations Sep 27, 2016 Issued
Array ( [id] => 15952737 [patent_doc_number] => 10664276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Remote command invocation using a register for storing a command and an attention bit indicating command has been issued [patent_app_type] => utility [patent_app_number] => 15/278265 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5160 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15278265 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/278265
Remote command invocation using a register for storing a command and an attention bit indicating command has been issued Sep 27, 2016 Issued
Array ( [id] => 12591351 [patent_doc_number] => 20180088946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR MIXING VECTOR OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/277963 [patent_app_country] => US [patent_app_date] => 2016-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15277963 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/277963
APPARATUSES, METHODS, AND SYSTEMS FOR MIXING VECTOR OPERATIONS Sep 26, 2016 Abandoned
Array ( [id] => 15284665 [patent_doc_number] => 10514997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Multi-producer single consumer lock-free queues with producer reference counting [patent_app_type] => utility [patent_app_number] => 15/277683 [patent_app_country] => US [patent_app_date] => 2016-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15277683 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/277683
Multi-producer single consumer lock-free queues with producer reference counting Sep 26, 2016 Issued
Array ( [id] => 15731117 [patent_doc_number] => 10613987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Operand cache coherence for SIMD processor supporting predication [patent_app_type] => utility [patent_app_number] => 15/274098 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15274098 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/274098
Operand cache coherence for SIMD processor supporting predication Sep 22, 2016 Issued
Array ( [id] => 14601031 [patent_doc_number] => 10353708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Strided loading of non-sequential memory locations by skipping memory locations between consecutive loads [patent_app_type] => utility [patent_app_number] => 15/273916 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5547 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273916 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273916
Strided loading of non-sequential memory locations by skipping memory locations between consecutive loads Sep 22, 2016 Issued
Array ( [id] => 16446791 [patent_doc_number] => 10838720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Methods and processors having instructions to determine middle, lowest, or highest values of corresponding elements of three vectors [patent_app_type] => utility [patent_app_number] => 15/274849 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 21890 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15274849 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/274849
Methods and processors having instructions to determine middle, lowest, or highest values of corresponding elements of three vectors Sep 22, 2016 Issued
Array ( [id] => 13752643 [patent_doc_number] => 10169268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Providing state storage in a processor for system management mode [patent_app_type] => utility [patent_app_number] => 15/270151 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270151 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270151
Providing state storage in a processor for system management mode Sep 19, 2016 Issued
Array ( [id] => 11365991 [patent_doc_number] => 20170003973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'Processor with Instruction Concatenation' [patent_app_type] => utility [patent_app_number] => 15/265184 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5345 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15265184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/265184
Execution of additional instructions prior to a first instruction in an interruptible or non-interruptible manner as specified in an instruction field Sep 13, 2016 Issued
Array ( [id] => 12213961 [patent_doc_number] => 09910770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Microcomputer having processor capable of changing endian based on endian information in memory' [patent_app_type] => utility [patent_app_number] => 15/197078 [patent_app_country] => US [patent_app_date] => 2016-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4001 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15197078 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/197078
Microcomputer having processor capable of changing endian based on endian information in memory Jun 28, 2016 Issued
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