Search

Amanda J. Barrow

Examiner (ID: 5901, Phone: (571)270-7867 , Office: P/1729 )

Most Active Art Unit
1729
Art Unit(s)
1729, 1795, 4111
Total Applications
786
Issued Applications
398
Pending Applications
78
Abandoned Applications
324

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20540265 [patent_doc_number] => 12557352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Forksheet transistor device with air gap spine [patent_app_type] => utility [patent_app_number] => 17/455938 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455938
Forksheet transistor device with air gap spine Nov 21, 2021 Issued
Array ( [id] => 17431976 [patent_doc_number] => 20220059685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => Cut-Fin Isolation Regions and Method Forming Same [patent_app_type] => utility [patent_app_number] => 17/453869 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7076 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453869 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453869
Cut-fin isolation regions and method forming same Nov 7, 2021 Issued
Array ( [id] => 18360125 [patent_doc_number] => 20230141716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => FINFETS HAVING VARIOUS DIFFERENT THICKNESSES OF GATE OXIDES AND RELATED APPARATUS, METHODS, AND COMPUTING SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/453727 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453727 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453727
Apparatuses including Finfets having different gate oxide configurations, and related computing systems Nov 4, 2021 Issued
Array ( [id] => 17431702 [patent_doc_number] => 20220059411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH POROUS DIELECTRIC STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/517566 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517566 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517566
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH POROUS DIELECTRIC STRUCTURE Nov 1, 2021 Abandoned
Array ( [id] => 19812460 [patent_doc_number] => 12243873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Integrated circuit having three-dimensional transistors and seal ring structure with monitoring pattern [patent_app_type] => utility [patent_app_number] => 17/488830 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9054 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488830
Integrated circuit having three-dimensional transistors and seal ring structure with monitoring pattern Sep 28, 2021 Issued
Array ( [id] => 20113222 [patent_doc_number] => 12363977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Forming dielectric sidewall and bottom dielectric isolation in Fork-FET devices [patent_app_type] => utility [patent_app_number] => 17/463019 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 31 [patent_no_of_words] => 1145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463019
Forming dielectric sidewall and bottom dielectric isolation in Fork-FET devices Aug 30, 2021 Issued
Array ( [id] => 20245969 [patent_doc_number] => 12426314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Strain generation and anchoring in gate-all-around field effect transistors [patent_app_type] => utility [patent_app_number] => 17/446479 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7485 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446479 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446479
Strain generation and anchoring in gate-all-around field effect transistors Aug 30, 2021 Issued
Array ( [id] => 18223311 [patent_doc_number] => 20230062305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => Mandrel Structures and Methods of Fabricating the Same in Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 17/460488 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460488 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460488
Mandrel structures and methods of fabricating the same in semiconductor devices Aug 29, 2021 Issued
Array ( [id] => 18227103 [patent_doc_number] => 20230066097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => ACTIVE REGION CUT PROCESS [patent_app_type] => utility [patent_app_number] => 17/461247 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461247 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461247
Active region cut process Aug 29, 2021 Issued
Array ( [id] => 19928232 [patent_doc_number] => 12302543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Integrated circuit device with reduced via resistance [patent_app_type] => utility [patent_app_number] => 17/461322 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 9711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461322 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461322
Integrated circuit device with reduced via resistance Aug 29, 2021 Issued
Array ( [id] => 19858321 [patent_doc_number] => 12261172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Semiconductor devices and methods of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 17/460198 [patent_app_country] => US [patent_app_date] => 2021-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460198
Semiconductor devices and methods of manufacturing thereof Aug 27, 2021 Issued
Array ( [id] => 18224045 [patent_doc_number] => 20230063039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 17/459784 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459784
Semiconductor devices and methods of manufacturing thereof Aug 26, 2021 Issued
Array ( [id] => 17295608 [patent_doc_number] => 20210391447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => Inner Spacer Formation in Multi-Gate Transistors [patent_app_type] => utility [patent_app_number] => 17/458087 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458087
Inner spacer formation in multi-gate transistors Aug 25, 2021 Issued
Array ( [id] => 19912569 [patent_doc_number] => 12288788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Integrated circuit devices [patent_app_type] => utility [patent_app_number] => 17/410326 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 5766 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410326 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/410326
Integrated circuit devices Aug 23, 2021 Issued
Array ( [id] => 17277903 [patent_doc_number] => 20210384101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/408988 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6616 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408988 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408988
Semiconductor package Aug 22, 2021 Issued
Array ( [id] => 19875105 [patent_doc_number] => 12267991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Multi-gate field-effect transistors in integrated circuits [patent_app_type] => utility [patent_app_number] => 17/399748 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 12376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399748 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399748
Multi-gate field-effect transistors in integrated circuits Aug 10, 2021 Issued
Array ( [id] => 19639710 [patent_doc_number] => 12170327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Semiconductor structure and manufacturing method of the same [patent_app_type] => utility [patent_app_number] => 17/398668 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398668 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398668
Semiconductor structure and manufacturing method of the same Aug 9, 2021 Issued
Array ( [id] => 18180911 [patent_doc_number] => 20230041640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/395879 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395879
Semiconductor structure and method for forming the same Aug 5, 2021 Issued
Array ( [id] => 19886956 [patent_doc_number] => 12272689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Semiconductor structure with composite oxide layer [patent_app_type] => utility [patent_app_number] => 17/389685 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389685
Semiconductor structure with composite oxide layer Jul 29, 2021 Issued
Array ( [id] => 18040214 [patent_doc_number] => 20220384431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/388005 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388005 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388005
Semiconductor device and method of forming the same Jul 28, 2021 Issued
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