Search

Amanda Karen Gurski

Examiner (ID: 11324, Phone: (571)270-5961 , Office: P/3623 )

Most Active Art Unit
3623
Art Unit(s)
3624, 3683, 3623, 3625
Total Applications
441
Issued Applications
121
Pending Applications
64
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20101298 [patent_doc_number] => 20250231234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => Latchup Detector and Clock Loss Detector [patent_app_type] => utility [patent_app_number] => 19/095150 [patent_app_country] => US [patent_app_date] => 2025-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19095150 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/095150
Latchup Detector and Clock Loss Detector Mar 30, 2025 Pending
Array ( [id] => 20589090 [patent_doc_number] => 20260074687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => METHODS AND SYSTEMS FOR REDUCING NOISE DURING SWITCH STATE TRANSITIONS [patent_app_type] => utility [patent_app_number] => 18/829165 [patent_app_country] => US [patent_app_date] => 2024-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18829165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/829165
METHODS AND SYSTEMS FOR REDUCING NOISE DURING SWITCH STATE TRANSITIONS Sep 8, 2024 Pending
Array ( [id] => 20291886 [patent_doc_number] => 20250317129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => CLOCK TRANSMISSION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/822480 [patent_app_country] => US [patent_app_date] => 2024-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18822480 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/822480
CLOCK TRANSMISSION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME Sep 2, 2024 Pending
Array ( [id] => 20182801 [patent_doc_number] => 20250266759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => CHARGE PUMP, CHARGE PUMP SYSTEM, AND METHOD OF CONTROLLING A CHARGE PUMP [patent_app_type] => utility [patent_app_number] => 18/821508 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821508 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/821508
CHARGE PUMP, CHARGE PUMP SYSTEM, AND METHOD OF CONTROLLING A CHARGE PUMP Aug 29, 2024 Pending
Array ( [id] => 19647174 [patent_doc_number] => 20240421694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => DRIVING CIRCUIT, DRIVING SYSTEM AND POWER CONVERSION DEVICE [patent_app_type] => utility [patent_app_number] => 18/815088 [patent_app_country] => US [patent_app_date] => 2024-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18815088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/815088
DRIVING CIRCUIT, DRIVING SYSTEM AND POWER CONVERSION DEVICE Aug 25, 2024 Pending
Array ( [id] => 19804838 [patent_doc_number] => 20250070763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => TOGGLE FLIP-FLOP AND COUNTER INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/812395 [patent_app_country] => US [patent_app_date] => 2024-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18812395 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/812395
TOGGLE FLIP-FLOP AND COUNTER INCLUDING THE SAME Aug 21, 2024 Pending
Array ( [id] => 19804865 [patent_doc_number] => 20250070790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => PHASE-LOCKED LOOP CIRCUIT, PHASE ERROR SIGN GENERATOR AND RFIC [patent_app_type] => utility [patent_app_number] => 18/808348 [patent_app_country] => US [patent_app_date] => 2024-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18808348 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/808348
PHASE-LOCKED LOOP CIRCUIT, PHASE ERROR SIGN GENERATOR AND RFIC Aug 18, 2024 Pending
Array ( [id] => 19620071 [patent_doc_number] => 20240405751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => DIGITAL VARIABLE REACTANCE ELEMENT, PHASE SHIFTER, AND IMPEDANCE MATCHING CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/802007 [patent_app_country] => US [patent_app_date] => 2024-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18802007 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/802007
DIGITAL VARIABLE REACTANCE ELEMENT, PHASE SHIFTER, AND IMPEDANCE MATCHING CIRCUIT Aug 12, 2024 Pending
Array ( [id] => 20551934 [patent_doc_number] => 12562737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Switch linearization with asymmetrical anti-series varactor pair [patent_app_type] => utility [patent_app_number] => 18/789400 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 3590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789400 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789400
Switch linearization with asymmetrical anti-series varactor pair Jul 29, 2024 Issued
Array ( [id] => 20476856 [patent_doc_number] => 20260019077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => DESKEW CIRCUIT AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/772700 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772700
DESKEW CIRCUIT AND METHOD FOR OPERATING THE SAME Jul 14, 2024 Pending
Array ( [id] => 19713418 [patent_doc_number] => 20250023560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => FAULT TOLERANT DRIVER CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/771275 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771275
FAULT TOLERANT DRIVER CIRCUIT Jul 11, 2024 Pending
Array ( [id] => 19713420 [patent_doc_number] => 20250023562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => INTEGRATED CIRCUIT FUNCTIONAL AT AND CAPABLE OF WITHSTANDING A MAXIMUM VOLTAGE GREATER THAN A RATED VOLTAGE, AND CORRESPONDING METHOD [patent_app_type] => utility [patent_app_number] => 18/761050 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761050 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/761050
INTEGRATED CIRCUIT FUNCTIONAL AT AND CAPABLE OF WITHSTANDING A MAXIMUM VOLTAGE GREATER THAN A RATED VOLTAGE, AND CORRESPONDING METHOD Jun 30, 2024 Pending
Array ( [id] => 20223618 [patent_doc_number] => 20250286549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => INTEGRATED CIRCUIT AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/756120 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756120 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756120
INTEGRATED CIRCUIT AND METHOD OF OPERATING THE SAME Jun 26, 2024 Pending
Array ( [id] => 19500986 [patent_doc_number] => 20240340004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => RF SWITCH STACK WITH CHARGE CONTROL ELEMENTS [patent_app_type] => utility [patent_app_number] => 18/749360 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749360 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749360
RF SWITCH STACK WITH CHARGE CONTROL ELEMENTS Jun 19, 2024 Pending
Array ( [id] => 20382493 [patent_doc_number] => 20250364986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => PROGRAMMABLE GATE VOLTAGE FOR ON RESISTANCE CONTROL OF POWER MODULE [patent_app_type] => utility [patent_app_number] => 18/672654 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672654 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672654
PROGRAMMABLE GATE VOLTAGE FOR ON RESISTANCE CONTROL OF POWER MODULE May 22, 2024 Pending
Array ( [id] => 19635372 [patent_doc_number] => 20240413821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => CIRCUIT AND SYSTEM FOR ACCELERATING RECOVERY OF INTEGRATED CIRCUIT AGING [patent_app_type] => utility [patent_app_number] => 18/648441 [patent_app_country] => US [patent_app_date] => 2024-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648441 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648441
CIRCUIT AND SYSTEM FOR ACCELERATING RECOVERY OF INTEGRATED CIRCUIT AGING Apr 27, 2024 Abandoned
Array ( [id] => 20637031 [patent_doc_number] => 12597920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Power switch circuit [patent_app_type] => utility [patent_app_number] => 18/632238 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1149 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632238
Power switch circuit Apr 9, 2024 Issued
Array ( [id] => 19516563 [patent_doc_number] => 20240348249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => POWER MOSFET DRIVER CIRCUIT ARRANGEMENT AND CORRESPONDING CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 18/630493 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630493 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/630493
POWER MOSFET DRIVER CIRCUIT ARRANGEMENT AND CORRESPONDING CONTROL METHOD Apr 8, 2024 Pending
Array ( [id] => 20284645 [patent_doc_number] => 20250309887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => CONTROLLING A POWER SWITCHING ELEMENT USING A SENSE SWITCHING ELEMENT [patent_app_type] => utility [patent_app_number] => 18/622369 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622369 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/622369
CONTROLLING A POWER SWITCHING ELEMENT USING A SENSE SWITCHING ELEMENT Mar 28, 2024 Pending
Array ( [id] => 19286696 [patent_doc_number] => 20240223176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => OPTIMIZATION OF POWER MODULE PERFORMANCE VIA PARASITIC MUTUAL COUPLING [patent_app_type] => utility [patent_app_number] => 18/429613 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429613 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429613
Optimization of power module performance via parasitic mutual coupling Jan 31, 2024 Issued
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