Search

Amanda Karen Gurski

Examiner (ID: 11324, Phone: (571)270-5961 , Office: P/3623 )

Most Active Art Unit
3623
Art Unit(s)
3624, 3683, 3623, 3625
Total Applications
441
Issued Applications
121
Pending Applications
64
Abandoned Applications
268

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8881532 [patent_doc_number] => 20130154716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'Circuit Topology for a Phase Connection of an Inverter' [patent_app_type] => utility [patent_app_number] => 13/686089 [patent_app_country] => US [patent_app_date] => 2012-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4559 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13686089 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/686089
Circuit topology for a phase connection of an inverter Nov 26, 2012 Issued
Array ( [id] => 8789500 [patent_doc_number] => 20130106469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'CONTROL CONTACT DRIVING SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/660638 [patent_app_country] => US [patent_app_date] => 2012-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6322 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13660638 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/660638
CONTROL CONTACT DRIVING SYSTEM Oct 24, 2012 Abandoned
Array ( [id] => 9419334 [patent_doc_number] => 20140103984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'QUADRATURE SYMMETRIC CLOCK SIGNAL GENERATION' [patent_app_type] => utility [patent_app_number] => 13/654328 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4461 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13654328 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/654328
QUADRATURE SYMMETRIC CLOCK SIGNAL GENERATION Oct 16, 2012 Abandoned
Array ( [id] => 10883321 [patent_doc_number] => 08907705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Fully integrated circuit for generating a ramp signal' [patent_app_type] => utility [patent_app_number] => 13/648557 [patent_app_country] => US [patent_app_date] => 2012-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3798 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13648557 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/648557
Fully integrated circuit for generating a ramp signal Oct 9, 2012 Issued
Array ( [id] => 9515856 [patent_doc_number] => 20140152348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'BICMOS CURRENT REFERENCE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/115630 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4887 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14115630 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/115630
BICMOS CURRENT REFERENCE CIRCUIT Sep 26, 2012 Abandoned
Array ( [id] => 9367984 [patent_doc_number] => 20140077857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'CONFIGURABLE DELAY CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/619765 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13619765 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/619765
CONFIGURABLE DELAY CIRCUIT Sep 13, 2012 Abandoned
Array ( [id] => 8718481 [patent_doc_number] => 20130069698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'RESET SIGNAL GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/619094 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7121 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13619094 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/619094
RESET SIGNAL GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME Sep 13, 2012 Abandoned
Array ( [id] => 9159322 [patent_doc_number] => 20130307599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'INPUT BUFFER' [patent_app_type] => utility [patent_app_number] => 13/615268 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3936 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13615268 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/615268
INPUT BUFFER Sep 12, 2012 Abandoned
Array ( [id] => 8583517 [patent_doc_number] => 20130002338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 13/606756 [patent_app_country] => US [patent_app_date] => 2012-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13038 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13606756 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/606756
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Sep 6, 2012 Abandoned
Array ( [id] => 8487428 [patent_doc_number] => 20120286835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'PLL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/555674 [patent_app_country] => US [patent_app_date] => 2012-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3306 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13555674 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/555674
PLL CIRCUIT Jul 22, 2012 Abandoned
Array ( [id] => 12102175 [patent_doc_number] => 09859274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Integrated circuit with at least two switches' [patent_app_type] => utility [patent_app_number] => 13/546555 [patent_app_country] => US [patent_app_date] => 2012-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 36 [patent_no_of_words] => 16487 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13546555 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/546555
Integrated circuit with at least two switches Jul 10, 2012 Issued
Array ( [id] => 8818985 [patent_doc_number] => 20130120030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'SEMICONDUCTOR DEVICE MEASURING VOLTAGE APPLIED TO SEMICONDUCTOR SWITCH ELEMENT' [patent_app_type] => utility [patent_app_number] => 13/541154 [patent_app_country] => US [patent_app_date] => 2012-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5421 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13541154 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/541154
SEMICONDUCTOR DEVICE MEASURING VOLTAGE APPLIED TO SEMICONDUCTOR SWITCH ELEMENT Jul 2, 2012 Abandoned
Array ( [id] => 10602705 [patent_doc_number] => 09323268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Low voltage isolation switch, in particular for a transmission channel for ultrasound applications' [patent_app_type] => utility [patent_app_number] => 13/538598 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4775 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13538598 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/538598
Low voltage isolation switch, in particular for a transmission channel for ultrasound applications Jun 28, 2012 Issued
Array ( [id] => 9324298 [patent_doc_number] => 08659325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Circuit and method for current-mode output driver with pre-emphasis' [patent_app_type] => utility [patent_app_number] => 13/532720 [patent_app_country] => US [patent_app_date] => 2012-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5851 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13532720 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/532720
Circuit and method for current-mode output driver with pre-emphasis Jun 24, 2012 Issued
Array ( [id] => 8450779 [patent_doc_number] => 20120261724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'STACKABLE PROGRAMMABLE PASSIVE DEVICE AND A TESTING METHOD' [patent_app_type] => utility [patent_app_number] => 13/529557 [patent_app_country] => US [patent_app_date] => 2012-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13529557 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/529557
Stackable programmable passive device and a testing method Jun 20, 2012 Issued
Array ( [id] => 11725913 [patent_doc_number] => 09698783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Driver integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/122623 [patent_app_country] => US [patent_app_date] => 2012-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5500 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14122623 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/122623
Driver integrated circuit May 23, 2012 Issued
Array ( [id] => 14860133 [patent_doc_number] => 10418809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Power management integrated circuit for driving inductive loads [patent_app_type] => utility [patent_app_number] => 13/453649 [patent_app_country] => US [patent_app_date] => 2012-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 8547 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13453649 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/453649
Power management integrated circuit for driving inductive loads Apr 22, 2012 Issued
Array ( [id] => 9763305 [patent_doc_number] => 08847636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Implementing voltage feedback gate protection for CMOS output drivers' [patent_app_type] => utility [patent_app_number] => 13/443209 [patent_app_country] => US [patent_app_date] => 2012-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3376 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13443209 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/443209
Implementing voltage feedback gate protection for CMOS output drivers Apr 9, 2012 Issued
Array ( [id] => 9278407 [patent_doc_number] => 20140028375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'SEMICONDUCTOR DEVICE, AND INVERTER, CONVERTER AND POWER CONVERSION DEVICE EMPLOYING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/110687 [patent_app_country] => US [patent_app_date] => 2012-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9963 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14110687 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/110687
Semiconductor device, and inverter, converter and power conversion device employing the same Apr 4, 2012 Issued
Array ( [id] => 13284335 [patent_doc_number] => 10153762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Method for controlling a semiconductor component [patent_app_type] => utility [patent_app_number] => 13/436380 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3974 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13436380 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/436380
Method for controlling a semiconductor component Mar 29, 2012 Issued
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