Search

Amanda Lee Bailey

Examiner (ID: 3862)

Most Active Art Unit
3673
Art Unit(s)
3673
Total Applications
484
Issued Applications
252
Pending Applications
47
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9160098 [patent_doc_number] => 20130308375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'Semiconductor Integrated Circuit for Low and High Voltage Operations' [patent_app_type] => utility [patent_app_number] => 13/954899 [patent_app_country] => US [patent_app_date] => 2013-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13954899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/954899
Semiconductor integrated circuit for low and high voltage operations Jul 29, 2013 Issued
Array ( [id] => 9470749 [patent_doc_number] => 08724392 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-13 [patent_title] => 'Controller management of memory array of storage device using magnetic random access memory (MRAM)' [patent_app_type] => utility [patent_app_number] => 13/952435 [patent_app_country] => US [patent_app_date] => 2013-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9820 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13952435 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/952435
Controller management of memory array of storage device using magnetic random access memory (MRAM) Jul 25, 2013 Issued
Array ( [id] => 9351377 [patent_doc_number] => 08670276 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-11 [patent_title] => 'Host-managed logical mass storage device using magnetic random access memory (MRAM)' [patent_app_type] => utility [patent_app_number] => 13/945362 [patent_app_country] => US [patent_app_date] => 2013-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3919 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13945362 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/945362
Host-managed logical mass storage device using magnetic random access memory (MRAM) Jul 17, 2013 Issued
Array ( [id] => 9351375 [patent_doc_number] => 08670274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-11 [patent_title] => 'Data storage in analog memory cells using modified pass voltages' [patent_app_type] => utility [patent_app_number] => 13/943131 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 12532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943131 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943131
Data storage in analog memory cells using modified pass voltages Jul 15, 2013 Issued
Array ( [id] => 10151641 [patent_doc_number] => 09183937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Method and apparatus for the erase suspend operation' [patent_app_type] => utility [patent_app_number] => 13/936620 [patent_app_country] => US [patent_app_date] => 2013-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2780 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13936620 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/936620
Method and apparatus for the erase suspend operation Jul 7, 2013 Issued
Array ( [id] => 9133422 [patent_doc_number] => 20130294136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'GLOBAL BIT LINE PRE-CHARGE CIRCUIT THAT COMPENSATES FOR PROCESS, OPERATING VOLTAGE, AND TEMPERATURE VARIATIONS' [patent_app_type] => utility [patent_app_number] => 13/935105 [patent_app_country] => US [patent_app_date] => 2013-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12990 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935105 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935105
Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations Jul 2, 2013 Issued
Array ( [id] => 9119828 [patent_doc_number] => 20130286750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'MEMORY SYSTEM AND CONTROL METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/924055 [patent_app_country] => US [patent_app_date] => 2013-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8016 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13924055 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/924055
Memory system and control method therefor Jun 20, 2013 Issued
Array ( [id] => 9591090 [patent_doc_number] => 08780643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Memory system and control method therefor' [patent_app_type] => utility [patent_app_number] => 13/924033 [patent_app_country] => US [patent_app_date] => 2013-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13924033 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/924033
Memory system and control method therefor Jun 20, 2013 Issued
Array ( [id] => 9106129 [patent_doc_number] => 20130279261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURAL MEMORY CELLS AND A DUMMY CELL COUPLED TO AN END OF A MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 13/919564 [patent_app_country] => US [patent_app_date] => 2013-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5569 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13919564 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/919564
Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell Jun 16, 2013 Issued
Array ( [id] => 9442509 [patent_doc_number] => 08711631 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-29 [patent_title] => 'Management of memory array with magnetic random access memory (MRAM)' [patent_app_type] => utility [patent_app_number] => 13/902650 [patent_app_country] => US [patent_app_date] => 2013-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4655 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13902650 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/902650
Management of memory array with magnetic random access memory (MRAM) May 23, 2013 Issued
Array ( [id] => 9066985 [patent_doc_number] => 20130258741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY' [patent_app_type] => utility [patent_app_number] => 13/900127 [patent_app_country] => US [patent_app_date] => 2013-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11957 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13900127 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/900127
Semiconductor device having multiport memory May 21, 2013 Issued
Array ( [id] => 9274677 [patent_doc_number] => 08638619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'High speed interface for multi-level memory' [patent_app_type] => utility [patent_app_number] => 13/872729 [patent_app_country] => US [patent_app_date] => 2013-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 8714 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13872729 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/872729
High speed interface for multi-level memory Apr 28, 2013 Issued
Array ( [id] => 9779701 [patent_doc_number] => 08854916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Semiconductor memory device and access method thereof' [patent_app_type] => utility [patent_app_number] => 13/862957 [patent_app_country] => US [patent_app_date] => 2013-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8972 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13862957 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/862957
Semiconductor memory device and access method thereof Apr 14, 2013 Issued
Array ( [id] => 8999862 [patent_doc_number] => 20130220986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'AUXILIARY POWER SUPPLY FOR A WELDING MACHINE' [patent_app_type] => utility [patent_app_number] => 13/860808 [patent_app_country] => US [patent_app_date] => 2013-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4636 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13860808 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/860808
Auxiliary power supply for a welding machine Apr 10, 2013 Issued
Array ( [id] => 10701570 [patent_doc_number] => 20160047716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'METHOD, COMPUTER PROGRAM PRODUCT & SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/781932 [patent_app_country] => US [patent_app_date] => 2013-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4358 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14781932 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/781932
METHOD, COMPUTER PROGRAM PRODUCT & SYSTEM Apr 4, 2013 Abandoned
Array ( [id] => 10409703 [patent_doc_number] => 20150294713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'STATIC RANDOM ACCESS MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 14/390455 [patent_app_country] => US [patent_app_date] => 2013-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3719 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14390455 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/390455
Static random access memory devices including a plurality of storage cells and a read/write circuit Apr 2, 2013 Issued
Array ( [id] => 9002020 [patent_doc_number] => 20130223145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'APPARATUS CONFIGURED TO PROGRAM A MEMORY CELL TO A TARGET THRESHOLD VOLTAGE REPRESENTING A DATA PATTERN OF MORE THAN ONE BIT' [patent_app_type] => utility [patent_app_number] => 13/852599 [patent_app_country] => US [patent_app_date] => 2013-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13852599 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/852599
Apparatus configured to program a memory cell to a target threshold voltage representing a data pattern of more than one bit Mar 27, 2013 Issued
Array ( [id] => 10673827 [patent_doc_number] => 20160019972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'Self-Timer For Sense Amplifier In Memory Device' [patent_app_type] => utility [patent_app_number] => 14/772047 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1355 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14772047 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/772047
Self-timer for sense amplifier in memory device Mar 14, 2013 Issued
Array ( [id] => 8978914 [patent_doc_number] => 20130212344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'SELECTIVE RETIREMENT OF BLOCKS' [patent_app_type] => utility [patent_app_number] => 13/833229 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6581 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13833229 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/833229
Selective retirement of blocks Mar 14, 2013 Issued
Array ( [id] => 9500997 [patent_doc_number] => RE044926 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2014-06-03 [patent_title] => 'Operational mode control in serial-connected memory based on identifier' [patent_app_type] => reissue [patent_app_number] => 13/774477 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5761 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774477 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/774477
Operational mode control in serial-connected memory based on identifier Feb 21, 2013 Issued
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